drvvd.c

mstar 776 开发的车载dvd

////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2006-2007 MStar Semiconductor, Inc.
// All rights reserved.
//
// Unless otherwise stipulated in writing, any and all information contained
// herein regardless in any format shall remain the sole proprietary of
// MStar Semiconductor Inc. and be kept in strict confidence
// (¨MStar Confidential Information〃) by the recipient.
// Any unauthorized act including without limitation unauthorized disclosure,
// copying, use, reproduction, sale, distribution, modification, disassembling,
// reverse engineering and compiling of the contents of MStar Confidential
// Information is unlawful and strictly prohibited. MStar hereby reserves the
// rights to any and all damages, losses, costs and expenses resulting therefrom.
//
////////////////////////////////////////////////////////////////////////////////

///
///@file drvVD.h
///@brief Scaler
///@author MStarSemi Inc.
///
///Scaler Control Scaler up or down to display.
///
///Features:
///- Automatic TV stand detection
///- 2-D comb filiter for NTSC/PAL
///- CVBS Video Out
///
///
///@par Example:
///@code
///  // VD Change source
///  void msAPI_VD_ChangeSource ( MS_SYS_INFO *penMsSysInfo )
///  {
///      // Set VD MUX
///      MDrv_ADC_SetVD_Mux(penMsSysInfo->enInputPortType);
///      // Program  Output &  Video's setting
///      MDrv_VD_ProgMultiInput( penMsSysInfo );
///      // VD MCU Reset
///      MDrv_VD_McuReset();
///  }
///@endcode
///

#define DRV_VD_C

/******************************************************************************/
/*                    Header Files                        */
/* ****************************************************************************/
#include <stdio.h>
#include <math.h>

#include "board.h"
#include "datatype.h"
#include "Sysinfo.h"
#include "hwreg.h"
#include "mreg51.h"
#include "drvmiu.h"
#include "panel.h"
#include "drvtimer.h"
#include "drvADC.h"
#include "drvSys.h"
#include "drvDLC.h"
#include "drvVD.h"


#define DRVVD_DBG(x) //x

#define REFER_TO_M3_VD            0
#define VD_SECAM_COLOR_KILL_EN    1

#define VD_DSP_VER 333


#if (MST_XTAL_CLOCK_HZ == FREQ_14P318MHZ)
#define BK_AFEC_21_VALUE		0x1A
#define BK_AFEC_8F_VALUE		0x15
#elif (MST_XTAL_CLOCK_HZ == FREQ_12MHZ)
#define BK_AFEC_21_VALUE		0x1C
#define BK_AFEC_8F_VALUE		0x19
#else
#error "Wrong Divider setting A"
#endif




void MDrv_VD_FinetuneComb(EN_VD_SIGNALTYPE enSignalType);

/********************************************************************************/
/*                     Local                    */
/* ******************************************************************************/
// initialize table
code MS_REG_TYPE astVdDecInitialize[] =
{
// AFEC init
    { BK_AFEC_0C, 0x00 },
    { BK_AFEC_18, 0x00 },
    { BK_AFEC_19, 0x00 },
    // { BK_AFEC_6F, 0x03 },
    // { BK_AFEC_7E, 0x00 },
    { BK_AFEC_15, 0x82 },
    { BK_AFEC_17, 0xF9 },
    { BK_AFEC_1E, 0x80 },
    { BK_AFEC_20, 0xB0 },
    { BK_AFEC_21, BK_AFEC_21_VALUE },
    { BK_AFEC_23, 0x84 },
    { BK_AFEC_26, 0x30 },
    { BK_AFEC_2A, 0x23 },
    { BK_AFEC_38, 0xD3 },
    { BK_AFEC_39, 0x6C },
    { BK_AFEC_3A, 0x1A },
    { BK_AFEC_3B, 0x7D },
    { BK_AFEC_3C, 0x0A },
    { BK_AFEC_3F, 0xC0 }, //        // 0x3F[3:0], FineGain[3:0]
    { BK_AFEC_40, 0x01 }, // 0x11   // 0x40[7:0], FineGain[12:4]
    { BK_AFEC_44, 0x80 }, // 0xC0   // 0x44[5:4], CoarseGain[1:0]
    { BK_AFEC_4E, 0x25 },
    { BK_AFEC_50, 0x80 },
    { BK_AFEC_55, 0x00 },
    { BK_AFEC_5A, 0x2F },
    { BK_AFEC_60, 0x15 },
    { BK_AFEC_66, 0x10 },
    { BK_AFEC_67, 0x17 },
//    { BK_AFEC_69, 0x00 }, // seven 070912_00
    { BK_AFEC_6B, 0xA6 },   // 0xA2 // kevin 20070815 for VCR
    { BK_AFEC_6C, 0xF4 },
    { BK_AFEC_70, 0xC4 },
    { BK_AFEC_72, 0x74 },
    { BK_AFEC_73, 0x50 },
    { BK_AFEC_76, 0x04 },
    { BK_AFEC_77, 0x07 },
    { BK_AFEC_79, 0x20 },
    { BK_AFEC_7D, 0x03 },
    { BK_AFEC_7F, 0x65 },
    { BK_AFEC_8F, BK_AFEC_8F_VALUE },
    { BK_AFEC_97, 0x05 },
    { BK_AFEC_98, 0x80 },
    { BK_AFEC_95, 0x26 },
    { BK_AFEC_07, 0xFA },
    { BK_AFEC_08, 0x1F },
    //{ BK_AFEC_69, 0x84 },  // 0x80 seven 070912_00
    { BK_AFEC_69, 0x80 },  // kevin 080104
    { BK_AFEC_A2, 0x90 }, // 0x02
    { BK_AFEC_A3, 0x01 },
    { BK_AFEC_A0, 0x34 },
    { BK_AFEC_A1, 0x6A },
    { BK_AFEC_A2, 0x90 }, // CJ
    { BK_AFEC_AA, 0x00 },
    { BK_AFEC_AB, 0x8F },
    { BK_AFEC_AE, 0xBE },
    { BK_AFEC_AF, 0x8D },
    { BK_AFEC_E3, 0x31 },
    { BK_COMB_10, 0x12 },
    { BK_COMB_13, 0x86 },
    { BK_COMB_1C, 0xBC },
    { BK_COMB_14, 0x04 },
    { BK_COMB_17, 0xB7 }, // 0xEA
    { BK_COMB_1B, 0x9B },
    { BK_COMB_20, 0x7D },
    { BK_COMB_21, 0x00 },
    { BK_COMB_22, 0x86 },
    { BK_COMB_2A, 0x04 },
    { BK_COMB_2B, 0x20 },
    { BK_COMB_2C, 0x04 },
    { BK_COMB_2E, 0x22 },
    { BK_COMB_30, 0xA3 },
    { BK_COMB_31, 0x25 },
    { BK_COMB_33, 0x30 },
    { BK_COMB_37, 0x88 },
    { BK_COMB_38, 0x18 },
    { BK_COMB_39, 0x00 },
    { BK_COMB_3A, 0x50 },
    { BK_COMB_40, 0x5C }, // 0x98
    { BK_COMB_4D, 0x90 },
    { BK_COMB_4E, 0x2C },
    { BK_COMB_52, 0x6F },
    { BK_COMB_53, 0x04 },
    { BK_COMB_57, 0x04 },
    { BK_COMB_58, 0x01 },
//    { BK_COMB_5A, 0x00 },
    { BK_COMB_63, 0xFE },
    { BK_COMB_64, 0x79 },
    { BK_COMB_65, 0xFD },
    { BK_COMB_66, 0x88 },
    { BK_COMB_67, 0x07 },
    { BK_COMB_68, 0x04 },
    { BK_COMB_69, 0xFD },
    { BK_COMB_6A, 0xF0 },
    { BK_COMB_6D, 0x02 },
    { BK_COMB_6E, 0x18 },
    { BK_COMB_70, 0xD0 },
    { BK_COMB_73, 0x80 },   // 2007/2/26
    { BK_COMB_74, 0x90 },   // 2007/2/26
    { BK_COMB_75, 0xD0 },   // 2007/2/26
    { BK_COMB_79, 0x00 },
    { BK_COMB_7E, 0xE0 },
    { BK_COMB_83, 0x0C },   // Set CTI off, 2007/2/26
    { BK_COMB_86, 0xF1 },
    { BK_COMB_87, 0x9B },
    { BK_COMB_88, 0x23 },
    { BK_COMB_89, 0xC7 },
    { BK_COMB_8A, 0x53 },
    { BK_COMB_8B, 0x0A },
    { BK_COMB_8D, 0x80 },
    { BK_COMB_8E, 0x80 },
    { BK_COMB_90, 0x31 },
    { BK_COMB_91, 0x33 },
    { BK_COMB_92, 0x71 },
    { BK_COMB_94, 0x40 },
    { BK_COMB_98, 0x2A },
    { BK_COMB_99, 0x80 },
    { BK_COMB_9A, 0x33 },
    { BK_COMB_9E, 0xC0 },
    { BK_COMB_9F, 0xC1 },
    { BK_COMB_AD, 0x60 },
    { BK_COMB_C0, 0x20 },
    { BK_COMB_C3, 0x1D },
    { BK_COMB_C4, 0x81 },

    { BK_COMB_D0, 0xBB },
    { BK_COMB_D1, 0x40 },
    { BK_COMB_D2, 0x40 },
    #if (PANEL_TYPE_SEL == Pnl_CPT07_DT)
    { BK_COMB_D3, 0x50 },
    #else
    { BK_COMB_D3, 0x60 },
    #endif

    { BK_COMB_DB, 0x32 },
    { BK_COMB_DD, 0x60 },
    { BK_COMB_DE, 0x00 },
    { BK_COMB_E0, 0xCC },
    { BK_COMB_E1, 0x54 },
    { BK_COMB_E2, 0x53 },
    { BK_COMB_E3, 0x01 },
    { BK_COMB_E4, 0x7E },
    { BK_COMB_E5, 0x7E },
    { BK_COMB_E6, 0x08 },
    { BK_COMB_E7, 0x75 },
    { BK_COMB_E8, 0x68 },
    { BK_COMB_E9, 0x6F },
    { BK_COMB_EA, 0x04 },
// SECAM init
    { BK_SECAM_01, 0x40 }, // 0x40
    { BK_SECAM_02, 0x92 }, // 0x92
    { BK_SECAM_03, 0xA2 }, // 0x9E
    { BK_SECAM_04, 0x2B }, // 0x2B
    { BK_SECAM_05, 0x64 }, // 0x64
    { BK_SECAM_07, 0xF0 }, // 0xF0
    { BK_SECAM_08, 0x01 }, // 0x01
    { BK_SECAM_09, 0x60 }, // 0x60
    { BK_SECAM_0A, 0x00 }, // 0xC0
    { BK_SECAM_0B, 0x42 }, // 0x41
    { BK_SECAM_0D, 0x05 }, // 0x04
    { BK_SECAM_0E, 0x65 }, // 0x64
    { BK_SECAM_11, 0xC0 }, // 0x00
    { BK_SECAM_12, 0x01 }, // 0x02
    { BK_SECAM_13, 0x00 }, // 0x00
    { BK_SECAM_14, 0xC0 }, // 0xC0
    { BK_SECAM_15, 0x3F }, // 0xBF
    { BK_SECAM_17, 0x07 }, // 0x07
    { BK_SECAM_20, 0x10 }, // 0x10
// VBI init
    { BK_VBI_2A, 0x23 },
//    { BK_VBI_41, 0x33 }, // CJ 0x52
    { BK_VBI_45, 0x60 },
//    { BK_VBI_50, 0x71 }, // CJ 0x72
//    { BK_VBI_51, 0xB3 }, // CJ 0xB2
    { BK_VBI_71, 0x80 },
    { BK_VBI_77, 0x1A },
    { BK_VBI_7C, 0x04 },
    { BK_VBI_7D, 0x17 },
    { BK_VBI_7E, 0x84 },
    { BK_VBI_7F, 0xF7 },
    { BK_VBI_81, 0x52 },
    { BK_VBI_86, 0xD6 },
    { BK_VBI_89, 0xC2 }, // 0x82
    { BK_VBI_8B, 0x0A }, // 0x04
    { BK_VBI_8D, 0xA5 }, // 0xE5
    { BK_VBI_C4, 0x32 },
    { BK_VBI_CB, 0xC4 },
    { BK_VBI_CC, 0xBD },
    { _END_OF_TBL_, 0x00 }
};

// VD Setting ----------------//
static xdata U8  u8BackupNoiseMag;
static xdata U8  u8SVflag;
static xdata U8  u8VideoSystem;
static xdata U8  u8AbnormalCounter;
static xdata U16 u16LatchH;
static xdata U16 u16DataH[3];
static xdata U8  u8HtotalDebounce;
static xdata U16 u16WSSinfo;
static xdata U8  u8WSSinfoCount;

code BYTE tVDtoCombTbl[33] =
{// VD Noise Mag
    0x04, // 0x00 //20060224 SEC
    0x04, // 0x01 //20060224 SEC
    0x04, // 0x02 //20060224 SEC
    0x0A, // 0x03
    0x0A, // 0x04
    0x0C, // 0x05
    0x0C, // 0x06
    0x0C, // 0x07
    0x0C, // 0x08
    0x0C, // 0x09
    0x0C, // 0x0A
    0x0C, // 0x0B
    0x0C, // 0x0C
    0x0C, // 0x0D
    0x0F, // 0x0E
    0x0F, // 0x0F
    0x0F, // 0x10
    0x0F, // 0x11
    0x0F, // 0x12
    0x0F, // 0x13
    0x0F, // 0x14
    0x0F, // 0x15
    0x0F, // 0x16
    0x0F, // 0x17
    0x0F, // 0x18
    0x0F, // 0x19
    0x0F, // 0x1A
    0x0F, // 0x1B
    0x0F, // 0x1C
    0x0F, // 0x1D
    0x0F, // 0x1E
    0x0F, // 0x1F
    0x0F  // 0x20
};

//----------------------------------//

#define MDrv_ReadByte_SH        MDrv_ReadByte
#define MDrv_Read2Byte_SH       MDrv_Read2Byte
#define MDrv_WriteByteMask_SH   MDrv_WriteByteMask
#define MDrv_WriteRegBit_SH     MDrv_WriteRegBit

/******************************************************************************/
/*                   Local Function Prototypes                                   */
/******************************************************************************/
/******************************************************************************/
/*                   Functions                                                */
/******************************************************************************/
/******************************************************************************/
///Setting registers from DSP's instructions, this is a backdoor to communicate
///between DSP and Housekeeping.
///DSP will indicate the following informations in registers:
///- BK_AFEC_DC: Ctrl
///- BK_AFEC_DE: Addr
///- BK_AFEC_DD: Mask
///- BK_AFEC_DF: Value
/******************************************************************************/
void MDrv_VD_SetRegFromDSP(void)
{
    U8  u8Ctl, u8Mask, u8Adr, u8Value;
    U16 u16Htotal, u16CurrentHStart, u16Temp;
    U8  u8AbnormalSignal;
    U8  u8update;

    u8Ctl = MDrv_ReadByte_SH( BK_AFEC_DC );

    if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_WRITE ) // write enable
    {
        u8Mask  = MDrv_ReadByte_SH( BK_AFEC_DD );
        u8Adr   = MDrv_ReadByte_SH( BK_AFEC_DE );
        u8Value = MDrv_ReadByte_SH( BK_AFEC_DF );

        if( ( u8Ctl & MSK_UD7_BANK ) == VAL_UD7_BANK6 ) // bank Comb
        {
            u16Temp = COMB_REG_BASE; // set base address to COMB_REG_BASE
        }
        else
        {
            u16Temp = AFEC_REG_BASE; // set base address to AFEC_REG_BASE
        }

        MDrv_WriteByteMask( u16Temp + u8Adr, u8Value, u8Mask );
        MDrv_WriteByteMask_SH( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE);
    }
    else if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_READ )
    {
        u8Mask = MDrv_ReadByte_SH( BK_AFEC_DD );
        u8Adr  = MDrv_ReadByte_SH( BK_AFEC_DE );
        if( ( u8Ctl & MSK_UD7_BANK) == VAL_UD7_BANK6 ) // bank Comb
        {
            u16Temp = COMB_REG_BASE; // set base address to COMB_REG_BASE
        }
        else
        {
            u16Temp = AFEC_REG_BASE; // set base address to AFEC_REG_BASE
        }

        u8Value = MDrv_ReadByte(u16Temp + u8Adr) & u8Mask;

        MDrv_WriteByteMask_SH( BK_AFEC_DF, u8Value, 0xFF );
        MDrv_WriteByteMask_SH( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE );
    }


    if( u8SVflag == 0 )
    {
        u16Htotal = MDrv_Read2Byte_SH(BK_AFEC_C7); // SPL_NSPL, H total

        DRVVD_DBG(("\r\nu8VideoSystem=%bu", u8VideoSystem));

        switch( u8VideoSystem ) // 2006.06.17 Michael, need to check SRC1 if we use MST6xxx
        {
            case SIG_NTSC: // 910
                 u16CurrentHStart = 910;