📄 drvscalertbl.c
字号:
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2006-2007 MStar Semiconductor, Inc.
// All rights reserved.
//
// Unless otherwise stipulated in writing, any and all information contained
// herein regardless in any format shall remain the sole proprietary of
// MStar Semiconductor Inc. and be kept in strict confidence
// (¨MStar Confidential Information〃) by the recipient.
// Any unauthorized act including without limitation unauthorized disclosure,
// copying, use, reproduction, sale, distribution, modification, disassembling,
// reverse engineering and compiling of the contents of MStar Confidential
// Information is unlawful and strictly prohibited. MStar hereby reserves the
// rights to any and all damages, losses, costs and expenses resulting therefrom.
//
////////////////////////////////////////////////////////////////////////////////
#include "drvAnalog_inline.h"
#include "fineTune.h"
#include "drvScaler.h"
#if (ENABLE_INPUT_PIP1 || ENABLE_INPUT_PIP2)// kevin 071101_0
MS_REG_INIT code DigitalPipCVBSTblInit[] =// kevin 071024_0
{
// Input Mux
_RV2(BK_IPMUX_01_L, 0x0021),
_RV2(BK_IPMUX_10_L, 0x0040),
// ATOP
_RV2(BK_ADC_ATOP_00_L, 0x0009),
_RV2(BK_ADC_ATOP_02_L, 0x00F0),// kevin 071102_4
_RV2(BK_ADC_ATOP_04_L, 0x0000),
_RV2(BK_ADC_ATOP_06_L, 0x0000),
// CHIPTOP
_RV2(BK_CHIPTOP_18_L, 0x0009),
_RV2(BK_CHIPTOP_1B_L, 0x0C00),
_RV2(BK_CHIPTOP_1F_L, 0x080C),
// OP2-PIP
_RV2(BK_OP2_PIP_00_L, 0xA03F),
//_RV2(BK_OP2_PIP_02_L, 0x83C0), 800x480
_RV2(BK_OP2_PIP_02_L, 0x842F),// kevin 071102_2 640x480
_RV2(BK_OP2_PIP_24_L, SUB_WIN_VSTART),
_RV2(BK_OP2_PIP_25_L, SUB_WIN_VHEIGHT),
_RV2(BK_OP2_PIP_26_L, SUB_WIN_HSTART),
_RV2(BK_OP2_PIP_27_L, SUB_WIN_HWIDTH),
// IP1 CH1
_RV1(BK_SELECT_00, REG_BANK_IP1F2),
_RV2(BK_SC_IP1F2_02_L, 0x0104),
_RV2(BK_SC_IP1F2_03_L, 0x849B),
_RV2(BK_SC_IP1F2_04_L, 0x002A),
_RV2(BK_SC_IP1F2_05_L, 0x0102),
_RV2(BK_SC_IP1F2_06_L, 0x01CA),
_RV2(BK_SC_IP1F2_07_L, 0x0528),
// IP2
_RV1(BK_SELECT_00, REG_BANK_IP2F2),
_RV2(BK_SC_IP2F2_04_L, 0xA000),
_RV2(BK_SC_IP2F2_05_L, 0x8013),
_RV2(BK_SC_IP2F2_0A_L, 0xA000),
// OP1
_RV1(BK_SELECT_00, REG_BANK_OP1),
_RV2(BK_SC_OP1_06_L, 0x0000),
_RV2(BK_SC_OP1_07_L, 0x0000),
_RV2(BK_SC_OP1_08_L, 0x0000),
_RV2(BK_SC_OP1_09_L, 0x0000),
// OP2
//_RV1(BK_SELECT_00, REG_BANK_VOP),
//_RV2(BK_SC_VOP_0C_L, 0x0438),
// TCON
_RV2(BK_TCON_2B_L, 0x6A46),
// IP1 CH0
_RV2(BK_IP1_16_02_L, 0x0100),
_RV2(BK_IP1_16_03_L, 0x849B),
_RV2(BK_IP1_16_04_L, 0x000C),
_RV2(BK_IP1_16_05_L, 0x006F),
_RV2(BK_IP1_16_06_L, PANEL_HEIGHT),
_RV2(BK_IP1_16_07_L, PANEL_WIDTH),
//_RV1(BK_IP1_16_09_L, PANEL_LOCK_Y_LINE),
_RV1(BK_IP1_16_09_L, 0x06),
_RV2(BK_IP1_16_1F_L, 0x0222),
_RV2(BK_IP1_16_21_L, 0x0001),
_RV2(BK_IP1_16_45_L, 0x0000),
// DNR
_RV1(BK_SELECT_00, REG_BANK_DNR),// kevin 071102_4
_RV2(BK_SC_DNR_60_L, 0x0008),
// AFEC
_RV2(0x351A, 0x8000),// kevin 071102_4
// COMB
_RV2(0x3610, 0x0012),// kevin 071102_4
_END_OF_TBL2_
};
#endif
MS_VIDEO_CAPTUREWINTABLE_TYPE code VideoCaptureWinTbl [] =
{
#if (VD_HT_TYPE==VD_HT_NORMAL)
{0x40, 0x09, MSVD_HACTIVE_NTSC, 480, MSVD_OVERSCAN_H_NTSC, MSVD_OVERSCAN_V_NTSC}, // NSTC
{0x6C, 0x0E, MSVD_HACTIVE_PAL, 576, MSVD_OVERSCAN_H_PAL, MSVD_OVERSCAN_V_PAL}, // PAL
{0x5E, 0x0E, MSVD_HACTIVE_SECAM, 576, MSVD_OVERSCAN_H_SECAM, MSVD_OVERSCAN_V_SECAM}, // SECAM
{0x62, 0x09, MSVD_HACTIVE_NTSC_443, 480, MSVD_OVERSCAN_H_NTSC_443, MSVD_OVERSCAN_V_NTSC_443}, // NTSC-443/PAL-60
{0x42, 0x09, MSVD_HACTIVE_PAL_M, 480, MSVD_OVERSCAN_H_PAL_M, MSVD_OVERSCAN_V_PAL_M}, // PAL-M
{0x49, 0x0E, MSVD_HACTIVE_PAL_NC, 576, MSVD_OVERSCAN_H_PAL_N, MSVD_OVERSCAN_V_PAL_N}, // PAL-Nc
#elif (VD_HT_TYPE==VD_HT_FIX1135)
{0xCC, 0x20-20, MSVD_HACTIVE_NTSC, 480, MSVD_OVERSCAN_H_NTSC, MSVD_OVERSCAN_V_NTSC}, // NSTC
{0xD2, 0x25-20, MSVD_HACTIVE_PAL, 576, MSVD_OVERSCAN_H_PAL, MSVD_OVERSCAN_V_PAL}, // PAL
{0xC4, 0x22-20, MSVD_HACTIVE_SECAM, 576, MSVD_OVERSCAN_H_SECAM, MSVD_OVERSCAN_V_SECAM}, // SECAM
{0xC4, 0x1F-20, MSVD_HACTIVE_NTSC_443, 480, MSVD_OVERSCAN_H_NTSC_443, MSVD_OVERSCAN_V_NTSC_443}, // NTSC-443/PAL-60
{0xCE, 0x1F-20, MSVD_HACTIVE_PAL_M, 480, MSVD_OVERSCAN_H_PAL_M, MSVD_OVERSCAN_V_PAL_M}, // PAL-M
{0xD9, 0x24-20, MSVD_HACTIVE_PAL_NC, 576, MSVD_OVERSCAN_H_PAL_N, MSVD_OVERSCAN_V_PAL_N}, // PAL-Nc
#elif (VD_HT_TYPE==VD_HT_MUL15)
{0x94, 0x0A, MSVD_HACTIVE_NTSC, 480, MSVD_OVERSCAN_H_NTSC, MSVD_OVERSCAN_V_NTSC}, // NSTC
{0xD3, 0x0E, MSVD_HACTIVE_PAL, 576, MSVD_OVERSCAN_H_PAL, MSVD_OVERSCAN_V_PAL}, // PAL
{0xBE, 0x0E, MSVD_HACTIVE_SECAM, 576, MSVD_OVERSCAN_H_SECAM, MSVD_OVERSCAN_V_SECAM}, // SECAM
{0xC4, 0x09, MSVD_HACTIVE_NTSC_443, 480, MSVD_OVERSCAN_H_NTSC_443, MSVD_OVERSCAN_V_NTSC_443}, // NTSC-443/PAL-60
{0x91, 0x09, MSVD_HACTIVE_PAL_M, 480, MSVD_OVERSCAN_H_PAL_M, MSVD_OVERSCAN_V_PAL_M}, // PAL-M
{0x9D, 0x0F, MSVD_HACTIVE_PAL_NC, 576, MSVD_OVERSCAN_H_PAL_N, MSVD_OVERSCAN_V_PAL_N}, // PAL-Nc
#endif
};
MS_VIDEO_CAPTUREWINTABLE_TYPE code ExtVDVideoCapture[] =
{
{0x00, 0x00, 720, 480, 50, 30 }, // NSTC
{0x00, 0x00, 720, 576, 50, 30 }, // PAL
{0x00, 0x00, 720, 576, 50, 30 }, // SECAM
{0x00, 0x00, 720, 480, 50, 30 }, // NTSC-443/PAL-60
{0x00, 0x00, 720, 480, 50, 30 }, // PAL-M
{0x00, 0x00, 720, 576, 50, 30 }, // PAL-Nc
};
U8 code astFreeRunColor[][3] =
{
// R, G, B
{ 0x00, 0x00, 0x00 }, // FREE_RUN_COLOR_BLACK
{ 0xFF, 0xFF, 0xFF }, // FREE_RUN_COLOR_WHITE
{ 0x00, 0x00, 0xFF }, // FREE_RUN_COLOR_BLUE
{ 0xFF, 0x00, 0x00 }, // FREE_RUN_COLOR_RED
};
#ifdef BOOT_JPEG_TEST
code MS_VIDEO_CAPTUREWINTABLE_TYPE astJPEGCapture[1]=
{
{0x0BA, 0x0012, 1320, 1000}// MD_1280x720_30P
};
#endif
MS_REG_INIT code MadiTbl60[]=
{
_RV1(BK_SELECT_00, REG_BANK_DNR),
_RV1(BK_SC_DNR_65_L, 0xF0),
_RV1(BK_SELECT_00, REG_BANK_OP1),
_RV2(BK_SC_OP1_2F_L, 0x8811),
_RV2(BK_SC_OP1_30_L, 0x9888),
_RV2(BK_SC_OP1_31_L, 0xBAA9),
_END_OF_TBL2_
};
MS_REG_INIT code MadiTbl50[]=
{
_RV1(BK_SELECT_00, REG_BANK_DNR),
_RV1(BK_SC_DNR_65_L, 0x94),
_RV1(BK_SELECT_00, REG_BANK_OP1),
_RV2(BK_SC_OP1_2F_L, 0x8811),
_RV2(BK_SC_OP1_30_L, 0x8888),
_RV2(BK_SC_OP1_31_L, 0x8988),
_END_OF_TBL2_
};
code U8 astScalerRegInit[] =
{
/* DNR */
_RV1(BK_SELECT_00, REG_BANK_DNR),
_RV3(BK_SC_DNR_12_L, MS_DNR_F2_BASE0), // dnr F2 base0
_RV3(BK_SC_DNR_14_L, MS_DNR_F2_BASE1), // dnr F2 base1
_RV2(BK_SC_DNR_16_L, 0x0400), // dnr F2 offset
_RV2(BK_SC_DNR_17_L, 0x02D0), // dnr F2 fetch
/* OPM */
_RV1(BK_SELECT_00, REG_BANK_OPM),
_RV3(BK_SC_OPM_26_L, MS_DNR_F2_BASE0), // opm base F2_0
_RV3(BK_SC_OPM_28_L, MS_DNR_F2_BASE1),
_RV2(BK_SC_OPM_2A_L, 0x0400),
_RV2(BK_SC_OPM_2B_L, 0x02D0),
/* VOP */
_RV1(BK_SELECT_00, REG_BANK_VOP),
_RV2(BK_SC_VOP_26_L, 0x0662),// Color Matrix
_RV2(BK_SC_VOP_27_L, 0x04a8),
_RV2(BK_SC_VOP_28_L, 0x0000),
_RV2(BK_SC_VOP_29_L, 0x1340),
_RV2(BK_SC_VOP_2A_L, 0x04a8),
_RV2(BK_SC_VOP_2B_L, 0x11a1),
_RV2(BK_SC_VOP_2C_L, 0x0000),
_RV2(BK_SC_VOP_2D_L, 0x04a8),
_RV2(BK_SC_VOP_2E_L, 0x0811),
_RV2(BK_SC_VOP_2F_L, 0x0015), // Enable CSC[4], range_cr[2], range_cb[0]
_RV1(BK_SELECT_00, REG_BANK_IP1F2),
_RV2(BK_SC_IP1F2_02_L, 0x0080), // enable no signal
#if ENABLE_NEW_VSYNC_MODE// kevin 071112_2
_RV2(BK_SC_IP1F2_09_L, 0x000F),
#else
_RV2(BK_SC_IP1F2_09_L, 0x0004), // early sample line
#endif
_RV1(BK_SELECT_00, REG_BANK_DNR),
_RV1(BK_SC_DNR_60_L, 0x00), // memory format
_RV1(BK_SELECT_00, REG_BANK_OPM),
_RV1(BK_SC_OPM_13_L, 0x21), // F1 Window
_RV1(BK_SELECT_00, REG_BANK_DNR),
_RV1(BK_SC_DNR_63_L, 0x30),
_RV1(BK_SC_DNR_64_L, 0x34),
_RV1(BK_SELECT_00, REG_BANK_OPM),
_RV1(BK_SC_OPM_25_H, 0x14),
_RV1(BK_SC_OPM_24_H, 0x4B),
_RV1(BK_SELECT_00, REG_BANK_VOP),
_RV1(BK_SC_VOP_48_L, 0x00), // disable *** important
_RV1(BK_SELECT_00, REG_BANK_IP1F2),
_RV1(BK_SC_IP1F2_08_L, 0x24), // For YCbCr go into frame buffer
// output control
_RV1(BK_SELECT_00, REG_BANK_VOP),
_RV1(BK_SC_VOP_11_L, 0x00), // lock coarse tune type 2
_RV1(BK_SELECT_00, REG_BANK_IP1F2),
_RV2(BK_SC_IP1F2_03_L, 0x0890), // b3: 10 bit input mode
_RV1(BK_SELECT_00, REG_BANK_VOP),
_RV2(BK_SC_VOP_22_L, 0x0000),
_RV1(BK_SC_VOP_1B_H, 0x2D),
_RV1(BK_SC_VOP_1C_L, 0x12), // dither method
#if NEW_LOCK
_RV1(BK_SC_VOP_1C_H, 0x01), // disable FL
#if 1 // FPLL specical setting for U01
_RV3(BK_LPLL_06_L, 0x00), // limit_d5d6d7[23:0]
_RV2(BK_LPLL_08_L, 0x0104), // limit_d5d6d7_RK[15:0]
_RV1(BK_LPLL_09_L, 0x03), // limit_d5d6d7_RK[23:16]
_RV2(BK_LPLL_0A_L, 0xFFF0), // limit_lpll_offset
_RV2(BK_LPLL_0B_L, 0x0B00), // tune coef & tune coef_RK, tune frame number
_RV2(BK_LPLL_1D_L, 0x000B), // fine tune coef_C & fine tune coef_RK
_RV1(BK_LPLL_1C_H, 0x00), // fine tune coef_C & fine tune coef_RK
_RV1(BK_LPLL_1E_L, 0x40),
#else
_RV3(BK_LPLL_06_L, 0x030104), // limit_d5d6d7[23:0]
_RV2(BK_LPLL_08_L, 0x0104), // limit_d5d6d7_RK[15:0]
_RV1(BK_LPLL_09_L, 0x03), // limit_d5d6d7_RK[23:16]
_RV2(BK_LPLL_0A_L, 0xFFF0), // limit_lpll_offset
_RV1(BK_LPLL_0B_H, 0xF1), // tune coef & tune coef_RK
_RV1(BK_LPLL_0B_L, 0x10), // tune frame number
_RV1(BK_LPLL_1D_L, 0xF1), // fine tune coef_C & fine tune coef_RK
_RV1(BK_LPLL_1C_H, 0x80), // fine tune coef_C & fine tune coef_RK
#endif
#endif
_RV1(BK_SELECT_00, REG_BANK_VOP),
_RV1(BK_SC_VOP_19_L, 0x01), // panel background color (Frame color enable)
_RV1(BK_SELECT_00, REG_BANK_IP1F2),
_RV1(BK_SC_IP1F2_0B_L, 0x02),
_RV1(BK_SC_IP1F2_0C_L, 0x00),
//
// Initialize Common table
//
// initialize auto adjust
_RV1(BK_SC_IP1F2_10_L, 0x01), // enable auto position
_RV1(BK_SC_IP1F2_19_L, 0x19), // enable auto phase, mask 6 bits
_RV1(BK_SC_IP1F2_0E_L, 0x00), // disable auto Gain
_RV1(BK_SC_IP1F2_18_H, 0x1C), // auto phase text threshold for BK0_8F
// 8/10 bit mode
_RV1(BK_SC_IP1F2_03_H, 0x84),
// VSync status
_RV1(BK_SELECT_00, REG_BANK_VOP),
_RV2(BK_SC_VOP_3B_L, 0x2030), // locking H total margin & locking SSC margin
// initial pre-scaling down by Scott recommand
_RV1(BK_SELECT_00, REG_BANK_IP2F2),
_RV1(BK_SC_IP2F2_01_L, 0x01), // enable HSD dither function
_RV1(BK_SC_IP2F2_03_L, 0x00), // For H pre-scaling down setting.
_RV1(BK_SC_IP2F2_07_L, 0x0F), // For V pre-scaling down setting.
_RV2(BK_SC_IP2F2_2C_L, 0x2074), // 2007/02/26, for color
_RV2(BK_SC_IP2F2_2D_L, 0x8082), // 2007/02/26, for color, this might be changed in other codes if ENABLE_PC_CSC=1
_RV1(BK_SELECT_00, REG_BANK_OP1_TEST),
_RV1(BK_SC_OP1_TEST_09_L, 0x01),// kevin 080130 // patch post V scaling (Hor. garbage in 2.5 De-interlace)
// the first V line is clear but latest V line is missed // changed to use 0x8 to let 1st and latest V line becomes half.
// Corng/LH limit for HSP
_RV1(BK_SELECT_00, REG_BANK_OP1),
_RV2(BK_SC_OP1_0A_L, 0x0104), // kevin 080121
_RV1(BK_SC_OP1_10_H, 0x0000), // 2007/3/4
_RV1(BK_SC_OP1_11_H, 0x0000),
_RV1(BK_SC_OP1_12_H, 0x0000),
_RV1(BK_SC_OP1_13_H, 0x0000),
_RV1(BK_SC_OP1_14_H, 0x0000),
_RV1(BK_SC_OP1_15_H, 0x0000),
_RV2(BK_SC_OP1_16_L, 0x0000), // post H initial factor [7..0]
_RV2(BK_SC_OP1_17_L, 0x0000),
_RV2(BK_SC_OP1_18_L, 0x0000),
_RV2(BK_SC_OP1_19_L, 0x0000),
_RV2(BK_SC_OP1_1A_L, 0x0000), // post V initial factor [7..0]
_RV2(BK_SC_OP1_1B_L, 0x0000),
_RV2(BK_SC_OP1_1C_L, 0x0000),
_RV2(BK_SC_OP1_1D_L, 0x0101),
_RV2(BK_SC_OP1_1E_L, 0x0000),
_RV2(BK_SC_OP1_1F_L, 0x0000),
_RV1(BK_SC_OP1_40_H, 0xA0), //For F2 Sub window
_RV2(BK_SC_OP1_41_L, 0x1010),
_RV2(BK_SC_OP1_42_L, 0x1010),
_RV2(BK_SC_OP1_43_L, 0x1010),
_RV1(BK_SELECT_00, REG_BANK_OPM),
_RV1(BK_SC_OPM_33_L, 0x01), // bit0:Pre32_Det
_RV1(BK_SELECT_00, REG_BANK_DNR),
_RV1(BK_SC_DNR_63_L, 0x02), // bit1:MAX_YCNR=1, bit0:PCNR_UV swap=0
// [3:2]:YCNR_Weighting=01b; TODO: need check
_RV1(BK_SC_DNR_64_L, 0x00),
_RV1(BK_SC_DNR_65_H, 0x12),
_RV1(BK_SC_DNR_1C_L, 0x81),
_RV1(BK_SELECT_00, REG_BANK_OP1),
_RV1(BK_SC_OP1_10_L, 0x0C),
_RV1(BK_SC_OP1_0D_L, 0x30),
//_RV1(BK_SC_OP1_14_H, 0x60),
//_RV1(BK_SC_OP1_15_L, 0x81),
_RV1(BK_SELECT_00, REG_BANK_OPM),
_RV1(BK_SC_OPM_15_H, 0x14),
_RV1(BK_SC_OPM_13_H, 0x08),
_RV1(BK_SC_OPM_14_H, 0x6D),
//SNR
_RV1(BK_SELECT_00, REG_BANK_OP1),
_RV1(BK_SC_OP1_1E_L, 0x0000),// b1: spatial NR enable // 20070304
_RV2(BK_SC_OP1_21_L, 0x0806),
_RV2(BK_SC_OP1_22_L, 0x69FC),
_RV2(BK_SC_OP1_23_L, 0x2345),
_RV2(BK_SC_OP1_24_L, 0x0011),
_RV2(BK_SC_OP1_25_L, 0x0000),
_RV2(BK_SC_OP1_26_L, 0x9B7D),
_RV2(BK_SC_OP1_27_L, 0x8769),
_RV1(BK_SC_OP1_28_L, 0x06),
_RV2(BK_SC_OP1_2C_L, 0x40F1),
_RV2(BK_SC_OP1_2D_L, 0x0020),
_RV2(BK_SC_OP1_52_L, 0x1248),
_RV2(BK_SC_OP1_0E_L, 0x0000),
//Enable HSP dither
_RV2(BK_SC_OP1_0C_L, 0x0080),
_RV1(BK_SELECT_00, REG_BANK_DNR),
_RV1(BK_SC_DNR_0C_H, 0x01),//DNR_MD_SEL
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -