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📄 drvscaler.c

📁 mstar 776 开发的车载dvd
💻 C
📖 第 1 页 / 共 5 页
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#if PANEL_ATCON
        MDrv_WriteByte(BK_DAC_03_L, 0xC0);
        MDrv_WriteByte(BK_DAC_03_H, 0x74); // seven 070823_00
        MDrv_WriteByte(BK_DAC_04_L, SET_BVOM_DC);
        MDrv_WriteByte(BK_DAC_04_H, 0x00); //VCOM DC LEVEL
        MDrv_WriteByte(BK_DAC_05_L, SET_BVOM_OUT);
        MDrv_WriteByte(BK_DAC_05_H, 0x00); //VCOM DC LEVEL
#elif PANEL_DTCON// kevin 20070831B
    #if (PANEL_TYPE_SEL == Pnl_TMD07_DT)
    MDrv_Write2Byte(BK_DAC_03_L, 0x000E);
    MDrv_Write2Byte(BK_DAC_04_L, 0x0039);
    MDrv_Write2Byte(BK_DAC_05_L, 0x0090);
    #else
    MDrv_Write2Byte(BK_DAC_03_L, 0x000E);
    MDrv_Write2Byte(BK_DAC_04_L, 0x0010);
    MDrv_Write2Byte(BK_DAC_05_L, 0x0000);
#endif
#endif
    }
    else if (devPanel_IsLVDS())// kevin 080114
    {
        MDrv_Write2Byte(BK_MOD_42_L, 0x1000);// kevin 081114_1
        MDrv_Write2Byte(BK_MOD_42_L, 0x0000 | LVDS_CURRENT_LEVEL);// kevin 081114_1
        MDrv_Write2Byte(BK_MOD_44_L, 0x0000);
        MDrv_Write2Byte(BK_MOD_45_L, 0x0010);
        MDrv_Write2Byte(BK_MOD_48_L, 0x0600 | LVDS_CURRENT_LEVEL_DOUBLE);// kevin 081114_1
        MDrv_Write2Byte(BK_MOD_49_L, 0x0040);
        MDrv_Write2Byte(BK_MOD_4A_L, 0x0000);
        MDrv_Write2Byte(BK_MOD_58_L, 0x0000);

        DRVSC_DBG(printf("Init LVDS"));
    }
    else
    {
        MDrv_WriteByte(BK_TCON_20_L, 0x0C);

        #if ENABLE_NEW_VSYNC_MODE// kevin 071112_2
        MDrv_WriteRegBit(BK_TCON_20_L, 0, _BIT2);
        #endif
    }

#if (ENABLE_DPWM_FUNCTION)
    {
        DRVSC_DBG(printf("\r\nInitial CCFL register..."));

        #if ENABLE_DPWM_LED//kevin
		MDrv_Write2Byte(BK_CCFL_00_L, 0x8000);// kevin 071106
		MDrv_Write2Byte(BK_CCFL_22_L, 0x00CF);// kevin 071106
		MDrv_Write2Byte(BK_CCFL_04_L, 0xEA0A);
		MDrv_Write2Byte(BK_CCFL_03_L, 0x0000|VSYNC_PWM_MODE_SEL);// kevin 071217 add
		MDrv_Write2Byte(BK_CCFL_06_L, VIN_STARTUP_H_THRD+(VIN_WRK_H_THRD<<8));// kevin 071217 add
		MDrv_Write2Byte(BK_CCFL_07_L, VIN_WRK_L_THRD+(VIN_STARTUP_L_THRD<<8));// kevin 071217 add
		MDrv_Write2Byte(BK_CCFL_0E_L, FB2_STARTUP);// kevin 071217 add
		MDrv_Write2Byte(BK_CCFL_0F_L, FB2_SET);
		MDrv_Write2Byte(BK_CCFL_10_L, FB2_CLAMP);// kevin n071217 add
		MDrv_Write2Byte(BK_CCFL_11_L, 0x00B4);
		MDrv_Write2Byte(BK_CCFL_12_L, 0x00B2);
		MDrv_Write2Byte(BK_CCFL_13_L, STRK1_CNT);
		MDrv_Write2Byte(BK_CCFL_14_L, 0x00B4);
		MDrv_Write2Byte(BK_CCFL_15_L, 0x00A4);
		MDrv_Write2Byte(BK_CCFL_16_L, STRK2_CNT);// kevin 071217 add
		MDrv_Write2Byte(BK_CCFL_1A_L, 0x0080);
		//MDrv_Write2Byte(BK_CCFL_1B_L, BURST_CLP);
		MDrv_Write2Byte(BK_CCFL_1C_L, BURST_DUTY);
		MDrv_Write2Byte(BK_CCFL_30_L, 0x2020);
		MDrv_Write2Byte(BK_CCFL_31_L, 0x00B3);// kevin 071218 add
		MDrv_Write2Byte(BK_CCFL_32_L, 0x0002);
		#else
		MDrv_Write2Byte(BK_CCFL_00_L, 0x8000);
		MDrv_Write2Byte(BK_CCFL_22_L, 0x00CF);
		MDrv_Write2Byte(BK_CCFL_03_L, 0x0000|VSYNC_PWM_MODE_SEL);
		MDrv_Write2Byte(BK_CCFL_06_L, VIN_STARTUP_H_THRD+(VIN_WRK_H_THRD<<8));
		MDrv_Write2Byte(BK_CCFL_07_L, VIN_WRK_L_THRD+(VIN_STARTUP_L_THRD<<8));
		MDrv_Write2Byte(BK_CCFL_09_L, 0x1200);
		MDrv_Write2Byte(BK_CCFL_0A_L, 0xFF38);
		MDrv_Write2Byte(BK_CCFL_0E_L, FB2_STARTUP);// kevin 071217 add
		MDrv_Write2Byte(BK_CCFL_0F_L, FB2_SET);
		MDrv_Write2Byte(BK_CCFL_10_L, FB2_CLAMP);   // kevin 071217 add
		MDrv_Write2Byte(BK_CCFL_13_L, STRK1_CNT);
		MDrv_Write2Byte(BK_CCFL_16_L, STRK2_CNT);
		//MDrv_Write2Byte(BK_CCFL_1B_L, BURST_CLP);// kevin 071217 add
		MDrv_Write2Byte(BK_CCFL_1C_L, BURST_DUTY);
		MDrv_Write2Byte(BK_CCFL_31_L, 0x00B3);
        #endif
    }
#endif
    // Enable Scaler Interrupt
    MDrv_Sys_SetInterrupt( EX1_DISP, ENABLE );

    MDrv_WriteByte(BK_SELECT_00, u8Bank);
}

//-----------------------------------------------------------------------------
// OP1 scaling ram code
//-----------------------------------------------------------------------------
void MDrv_Scaler_InitFilterTbl(MS_SCALING_DRAM dram, MS_SCALING_FILTER filter)
{
    U16 i, j;
    U8 ramcode[5];
    U8 u8Bank;

    u8Bank = MDrv_ReadByte(BK_SELECT_00);
    MDrv_WriteByte(BK_SELECT_00, REG_BANK_OP1);

    if(dram == MST_SCALING_SRAM1)
        MDrv_WriteRegBit(BK_SC_OP1_72_L, 1, _BIT0);// ram select L
    else
        MDrv_WriteRegBit(BK_SC_OP1_72_L, 1, _BIT1);// ram select H


    for(i=0; i< SCALING_FLT_ENTRY; i++)
    {
        while(MDrv_ReadByte(BK_SC_OP1_72_L) & _BIT7); // wait until previous write complete
        MDrv_WriteByte(BK_SC_OP1_71_L, i); //address

        for(j=0; j<5; j++)
        {
            ramcode[j] = ScalingFilterTable[filter][i*5 +j];
        }

        // data
        MDrv_WriteByte(BK_SC_OP1_73_L, ramcode[0]);
        MDrv_WriteByte(BK_SC_OP1_73_H, ramcode[1]);
        MDrv_WriteByte(BK_SC_OP1_74_L, ramcode[2]);
        MDrv_WriteByte(BK_SC_OP1_74_H, ramcode[3]);
        MDrv_WriteByte(BK_SC_OP1_75_L, ramcode[4]);

        MDrv_WriteRegBit(BK_SC_OP1_72_L, 1, _BIT7); //enable write
    }

    MDrv_Write2Byte(BK_SC_OP1_72_L, 0x0000);
    MDrv_WriteByte(BK_SELECT_00, u8Bank);
}

void MDrv_Scaler_Get_FilterTbl(MS_SCALING_DRAM dram)
{
    U16 i;
    U8 ramcode[5];
    U8 u8Bank;

    u8Bank = MDrv_ReadByte(BK_SELECT_00);
    MDrv_WriteByte(BK_SELECT_00, REG_BANK_OP1);

    if(dram == MST_SCALING_SRAM1)
        MDrv_WriteRegBit(BK_SC_OP1_72_L, 1, _BIT0);// ram select L
    else
        MDrv_WriteRegBit(BK_SC_OP1_72_L, 1, _BIT1);// ram select H

    for(i=0; i< SCALING_FLT_ENTRY; i++)
    {
        while(MDrv_ReadByte(BK_SC_OP1_72_H) & _BIT7); // wait until previous read complete

        MDrv_WriteByte(BK_SC_OP1_71_L, i); // assign address

        MDrv_WriteRegBit(BK_SC_OP1_72_H, 1, _BIT7); //enable read

        if(dram == MST_SCALING_SRAM1)
        {
            ramcode[0] = MDrv_ReadByte(BK_SC_OP1_76_L);
            ramcode[1] = MDrv_ReadByte(BK_SC_OP1_76_H);
            ramcode[2] = MDrv_ReadByte(BK_SC_OP1_77_L);
            ramcode[3] = MDrv_ReadByte(BK_SC_OP1_77_H);
            ramcode[4] = MDrv_ReadByte(BK_SC_OP1_78_L);
        }
        else
        {
            ramcode[0] = MDrv_ReadByte(BK_SC_OP1_78_H);
            ramcode[1] = MDrv_ReadByte(BK_SC_OP1_79_L);
            ramcode[2] = MDrv_ReadByte(BK_SC_OP1_79_H);
            ramcode[3] = MDrv_ReadByte(BK_SC_OP1_7A_L);
            ramcode[4] = MDrv_ReadByte(BK_SC_OP1_7A_H);
        }
        SCALER_D_DBG(printf("Ram Code %x: %bx, %bx, %bx, %bx, %bx \r\n", i, ramcode[0], ramcode[1], ramcode[2], ramcode[3], ramcode[4], ramcode[5]));
    }

    MDrv_Write2Byte(BK_SC_OP1_72_L, 0x0000);
    MDrv_WriteByte(BK_SELECT_00, u8Bank);
}

void MDrv_Scaler_InitVariable(void)
{
    g_SrcInfo.u16H_DisStart = 0;
    g_SrcInfo.u16V_DisStart = 0;
    g_SrcInfo.u16H_DisSize  = 0;
    g_SrcInfo.u16V_DisSize  = 0;

    /* DE */
    g_SrcInfo.u8DE_V_Start = devPanel_DE_VSTART();
    g_SrcInfo.u16DE_V_End =  devPanel_DE_VSTART() + devPanel_HEIGHT() - 1;

    g_SrcInfo.u16ColorFinetuneFlag &= ~FINETUNE_3DNR;

    MDrv_ACE_Init_Variable();
    MDrv_ACE_Set_Matrix(tSRGB, tDefaultColorCorrectionMatrix);
}

void MDrv_Scaler_InitRegInTimingChange(void)
{
    U8 u8Bank;

    u8Bank = MDrv_ReadByte(BK_SELECT_00);
    MDrv_WriteByte(BK_SELECT_00, REG_BANK_IP1F2);

    MDrv_WriteByte(BK_SC_IP1F2_21_L, 0x00);

    MDrv_WriteByte(BK_SELECT_00, u8Bank);
}

//-----------------------------------------------------------------------------
// MOD
//-----------------------------------------------------------------------------

void MDrv_MOD_PowerOn(void)
{
    U16 u16MOD_LVDS;
    U16 u16MOD_TTL;
    BOOLEAN bEnable;

    if (devPanel_IsLVDS())
    {
        //MDrv_WriteByteMask(BK_MOD_48_L, _BIT4| _BIT3|_BIT2,  _BIT4|_BIT3|_BIT2);
        MDrv_WriteByteMask(BK_MOD_48_L, _BIT3|_BIT2,  _BIT3|_BIT2);
        MDrv_WriteByteMask(BK_MOD_45_L, 0x3F, 0x3F);
        MDrv_Write2Byte(BK_MOD_44_L, MOD_LVDS_GPIO);
        u16MOD_LVDS = (PANEL_CONNECTOR_SWAP_LVDS_CH & _BIT6) | (PANEL_CONNECTOR_SWAP_LVDS_POL & _BIT5) | (PANEL_LVDS_TI_MODE & _BIT2);

        // Dual panel setting
        bEnable = devPanel_Is_DUAL_PORT();
        MDrv_WriteRegBit(BK_MOD_4A_L, bEnable, _BIT1);
        bEnable = devPanel_Is_ChannelSwap();
        MDrv_WriteRegBit(BK_MOD_4A_L, bEnable, _BIT0);

        u16MOD_TTL = 0;
    }
    else // TTL
    {
        MDrv_WriteByteMask(BK_MOD_48_L, 0, _BIT4|_BIT3|_BIT2);
        MDrv_WriteByteMask(BK_MOD_45_L, 0x00, 0x3F);
        MDrv_Write2Byte(BK_MOD_44_L, 0xFFF);
        u16MOD_TTL = 0;
        u16MOD_TTL |= ( (PANEL_DITHER) ? _BIT6 : _BIT7 );
        if( PANEL_SWAP_ODD_RB ) u16MOD_TTL |= _BIT11;
        if( PANEL_SWAP_ODD_ML ) u16MOD_TTL |= _BIT12;
        if( PANEL_SWAP_EVEN_RB ) u16MOD_TTL |= _BIT13;
        if( PANEL_SWAP_EVEN_ML ) u16MOD_TTL |= _BIT14;

        u16MOD_LVDS = 0;
    }

    MDrv_WriteByteMask(BK_MOD_40_L, u16MOD_LVDS, _BIT6|_BIT5|_BIT2);

    MDrv_Write2Byte( BK_MOD_49_L, u16MOD_TTL );

    if (devPanel_Is_ANALOG_TCON())
    {   // ATCON output enable
        MDrv_Write2Byte(BK_MOD_57_L, 0x0000);
        MDrv_Write2Byte(BK_MOD_59_L, 0x0010); // Selection ATCON pad.
    }
    else if (devPanel_IsTCON())
    {   // DTCON output enable
        MDrv_Write2Byte( BK_MOD_58_L, SET_DTCON_OEN & 0x3FF );
        MDrv_WriteByte( BK_MOD_59_L, SET_DTCON_SEL & 0x0F );

		#if PANEL_DTCON
        MDrv_WriteByteMask(BK_MOD_4A_L, 0x00, 0x1C);
        MDrv_WriteByteMask(BK_MOD_4A_L, ((SET_MOD_INV_CLK << 4) | (SET_MOD_INV_VSYNC << 3) | (SET_MOD_INV_DE << 2)), 0x1C);

        MDrv_WriteByteMask(BK_MOD_4A_H, 0x00, 0x10);
        MDrv_WriteByteMask(BK_MOD_4A_H, (SET_MOD_INV_HSYNC << 4), 0x10);
		#endif
    }
}

void MDrv_MOD_PowerOff(void)
{
    MDrv_WriteByteMask(BK_MOD_48_L, 0, _BIT4|_BIT3|_BIT2);
    MDrv_WriteByteMask(BK_MOD_45_L, 0x3F, 0x3F); // set [5:0]
    MDrv_Write2Byte(BK_MOD_44_L, 0xFFF);

    if (devPanel_Is_ANALOG_TCON())
    {   // ATCON output disalbe
        MDrv_Write2Byte(BK_MOD_57_L, 0x7FFF);
    }
    else if (devPanel_IsTCON())
    {   // DTCON output disable
        MDrv_Write2Byte(BK_MOD_58_L, 0x03FF);
    }
}

//-----------------------------------------------------------------------------
// DAC
//-----------------------------------------------------------------------------

void MDrv_DAC_PowerOn(void)
{
    // XXX DAC bank is unknown
    MDrv_WriteByteMask(BK_DAC_00_L, 0x8F, 0x8F);
}

void MDrv_DAC_PowerOff(void)
{
    // XXX DAC bank is unknown
    MDrv_WriteByteMask(BK_DAC_00_L, 0x00, 0x8F);
}

//-----------------------------------------------------------------------------
// panel
//-----------------------------------------------------------------------------

void MDrv_Scaler_SetPanelVCC(BOOLEAN bEnable)
{
    // ToDo
    if(bEnable)
    {
        Panel_VCC_ON();
        stSystemInfo.u8PanelPowerStatus |= PANEL_POWER_VCC;
    }
    else
    {
        Panel_VCC_OFF();
        stSystemInfo.u8PanelPowerStatus &= ~PANEL_POWER_VCC;
    }
}

void MDrv_Scaler_SetPanelBacklight(BOOLEAN bEnable)
{
    // ToDo
    if(bEnable)
    {
        Panel_Backlight_VCC_ON();
        stSystemInfo.u8PanelPowerStatus |= PANEL_POWER_LIGHT_ON;
    }
    else
    {
        Panel_Backlight_VCC_OFF();
        stSystemInfo.u8PanelPowerStatus &= ~PANEL_POWER_LIGHT_ON;
    }
}

U32 g_u32LVDSDataEnableTime = 0;
BOOLEAN g_bIsPanelOnTimingCheckValid = 0;

void MDrv_Scaler_SetPanelOnOff(BOOLEAN bPanelOn)
{
    U8 u8Bank;
    U32 delayTime;

    /* enable/disable VCC */
    if(bPanelOn)
    {
        MDrv_Scaler_SetPanelVCC(bPanelOn);
        delayTime = pnlGetOnTiming1();
    }
    else
    {
        SetPanelBacklight(bPanelOn);
        delayTime = pnlGetOffTiming1();

#if (ENABLE_DPWM_FUNCTION)
        MDrv_Write2Byte(BK_CCFL_02_L, 0x0000);
#endif
    }

    MDrv_Timer_Delayms(delayTime);

    /* set VOP */
    u8Bank = MDrv_ReadByte(BK_SELECT_00);
    MDrv_WriteByte(BK_SELECT_00, REG_BANK_VOP);

    if (bPanelOn)
    {
        if (devPanel_IsLVDS())
            MDrv_WriteByte(BK_SC_VOP_22_L, 0x11);
        else
            MDrv_WriteByte(BK_SC_VOP_22_L, 0x00);

        MDrv_WriteByte(BK_SC_VOP_46_H, 0x40);

        MDrv_MOD_PowerOn();

        if (devPanel_IsTCON()||(devPanel_Is_ANALOG_TCON()))
        {
            MDrv_WriteByte(BK_TCON_20_H, SET_PTC_MODE2);

            MDrv_WriteByte(BK_TCON_20_L, SET_PTC_MODE1);		// Enable TCON

            #if ENABLE_NEW_VSYNC_MODE// kevin 071112_2
            MDrv_WriteRegBit(BK_TCON_20_L, 0, _BIT2);
            #endif
        }
    }
    else

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