📄 drvanalog_datatype.h
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#ifndef _DRV_ANALOG_DATATYPE_H_
#define _DRV_ANALOG_DATATYPE_H_
#include "DataType.h"
#include "board.h"
////
////
// H_SaclingRatioInfo/V_SaclingRatioInfo
#define PRE_SCALING_NONE 0x00
#define PRE_SCALING_DOWN 0x01
#define POST_SCALING_NONE 0x00
#define POST_SCALING_UP 0x01
#define POST_SCALING_DOWN 0x02
#define POST_SCALING_DOWN_CB 0x03
#define SCALING_TYPE_NONE 0
#define SCALING_TYPE_PRE_POST 1
//------------------------------------------------------------------------------
// Scaler filter
//
// The total bit of SRAM code is 40bits and 64 entries
// The regiser size of Lola is 8 bits. Hence the size of
// 8 bits array is 64*40/8 = 320
#define SCALING_FLT_ENTRY 64
#define SCALING_FLT_SIZE 320
#define VIDEO_POLLING_FLAG_DOMODE_SETTING _BIT0
#define VIDEO_POLLING_FLAG_MUTE _BIT1
#define VIDEO_POLLING_FLAG_MODE_DONE _BIT2
#define VD_DATA_VALID _BIT0
#define MD_HTOTAL_TORLANCE 10 //horizontal total torlance
// mode change torlance
#define MD_HPERIOD_TORLANCE 10 // horizontal period torlance
#define MD_VTOTAL_TORLANCE 10 // vertical total torlance
#define MD_HDE_TORLANCE 5
#define MD_VDE_TORLANCE 5
#define MD_HFREQ_TORLANCE 15 // Unit: 0.1kHz
#define MD_VFREQ_TORLANCE 15 // Unit: 0.1Hz
#define MD_FREQ_DELTA 100 // search the user mode
#define HDTV 1
#define SDTV 0
// video decoder status
#define VD_SYNC_LOCKED _BIT15
#define VD_HSYNC_LOCKED _BIT14
#define VD_INTERLACED _BIT13
#define VD_VSYNC_50HZ _BIT12
#define VD_RESET_ON _BIT11
#define VD_COLOR_LOCKED _BIT10
#define VD_PAL_SWITCH _BIT9
#define VD_FSC_TYPE (_BIT7|_BIT6|_BIT5)
#define VD_FSC_3579 (_BIT6) // NTSC
#define VD_FSC_3575 (_BIT7) // PAL(M)
#define VD_FSC_3582 (_BIT7|_BIT6) // PAL(Nc)
#define VD_FSC_4433 (0) // PAL or NTSC443
#define VD_FSC_4285 (_BIT5) // SECAM
#define VD_VCR_MODE _BIT4
#define VD_VCR_PAUSE _BIT3
#define VD_MACROVISION _BIT2
#define VD_STATUS_RDY _BIT0
#define VD_MODE_DETECT_MASK (VD_HSYNC_LOCKED|VD_VSYNC_50HZ|VD_FSC_TYPE|VD_RESET_ON)
#define VD_525_LINE 0x10
#define VD_625_LINE 0x20
#define VD_UNKNOWN 0xFF
#define MD_VSYNC_POR_BIT _BIT0 // VSnc polarity bit(0/1 = positive/negative)
#define MD_HSYNC_POR_BIT _BIT1 // HSync polarity bit(0/1 = positive/negative)
#define MD_HSYNC_LOSS_BIT _BIT2 // HSync loss bit
#define MD_VSYNC_LOSS_BIT _BIT3 // VSync loss bit
#define MD_INTERLACE_BIT _BIT4 // Interlace mode
#define MD_USER_MODE_BIT _BIT7 // User new mode (Not found in mode table)
#define MD_SYNC_LOSS (MD_HSYNC_LOSS_BIT | MD_VSYNC_LOSS_BIT)
#define IsSrcHDTVMode() ((g_SrcInfo.u8DisplayStatus& DISPLAYWINDOW_HDTV) == DISPLAYWINDOW_HDTV)
#define PANEL_POWER_VCC 0x01
#define PANEL_POWER_LIGHT_ON 0x02
#define PANEL_POWER_BLUESCREEN 0x04
#define TN_FREQ_SS_INVERSE 16 // 1/0.0625
#define TN_RSA_RSB 0x06
#define TN_FREQ_SS 62.5 // kHz
//------------------------------------------------------------------------------
// Scaler
//
/// Reset type
typedef enum
{
RST_SCALER_ALL = _BIT0,
RST_IP_F1 = _BIT1,
RST_IP_F2 = _BIT2,
RST_OP = _BIT3,
RST_IP_ALL = _BIT4,
RST_CLK = (_BIT6|_BIT3),
// some SW Reset for ADCDVIPLL block
RST_ATOP = (_BIT7 << 8),
RST_PLL_DIG_B = (_BIT3 << 8),
RST_ADC_DIG_B = (_BIT2 << 8),
RST_PLL_DIG_A = (_BIT1 << 8),
RST_ADC_DIG_A = (_BIT0 << 8),
RST_PLL = ( RST_PLL_DIG_B | RST_PLL_DIG_A ),
RST_ADC = ( RST_ADC_DIG_B | RST_ADC_DIG_A ),
}MS_SOFTWARE_REST_TYPE;
/// Memory format
typedef enum
{
MS_MEM_FMT_NO_USE,
MS_MEM_FMT_422,
MS_MEM_FMT_444,
MS_MEM_FMT_MAIN_422_SINGLE_BUF,
} MS_MEMORY_TYPE;
/// Deinterlace mode
typedef enum
{
MS_DEINT_OFF,
MS_DEINT_2DDI_BOB,
MS_DEINT_2P5DDI,// kevin 080128
} MS_DEINTERLACE_MODE;
/// EODI mode
typedef enum
{
MS_EODI_OFF,
MS_EODI_2D,
} MS_EODI_MODE;
/// status of set mode
typedef enum
{
MS_SETMODE_DONOTHING,
MS_SETMODE_SUCCESS, ///< set mode success
MS_SETMODE_INVALIDTIMING, ///< invalid timing
MS_SETMODE_NOSIGNAL, ///< no signal
MS_SETMODE_NOINPUTSOURCETYPE, ///< no inpupt source type
} MS_SETMODE_STATUS;
//// Scaling filter
typedef enum
{
#if 0// kevin 20070910
SCALING_121,
SCALING_2121,
#else
SCALING_BS_G11, // Bsplin + gain 1.1
SCALING_SYNC,
SCALING_121G2266G1030_CUBIC, // sdramLP121G2266G1030_cubic.dat
#endif
/*
SCALING_121G2266G1030_SPLINE, // sdramLP121G2266G1030_spline.dat
SCALING_121G2300G1030_CUBIC, // sdramLP121G2300G1030_cubic.dat
SCALING_BSPLINE_NOG,
SCALING_BSPLINE_ENHANCE,
SCALING_BSPLINE_EQUAL_COEF,
SCALING_VERTICAL_PEAKING_266, // 0.3_2.66
SCALING_VERTICAL_NATIONAL_1, // Kuan national stadard 1080i setting 1
SCALING_VERTICAL_NATIONAL_2, // Kuan national stadard 1080i setting 2
SCALING_CUBIC_3_10_3,
*/
SCALING_MAX
} MS_SCALING_FILTER;
/// Scaling DRAM
typedef enum
{
MST_SCALING_SRAM1,
MST_SCALING_SRAM2,
MST_SCALING_SRAM_NUM
}MS_SCALING_DRAM;
//------------------------------------------------------------------------------
// Scaler NR
//
typedef enum
{
MS_NR_ON,
MS_NR_OFF,
}MS_NR_FUNCTION_TYPE;
typedef enum
{
MS_DNR_ON = 0,
MS_DNR_FORCE_PRE = 1,
MS_DNR_OFF = 2,
}MS_DNR_FUNCTION_TYPE;
typedef enum
{
MS_NR_FORCE_8BITS,
MS_NR_FORCE_10BITS,
MS_NR_FORCE_OFF,
}MS_NR_BIT_TYPE;
//------------------------------------------------------------------------------
// FPLL
//
typedef enum
{
FPLL_STOP, ///< 0:Stop
FPLL_TUNE_LINE_ONLY, ///< 1:Line Only
FPLL_TUNE_CLK_LINE_FOR_PC_YPBPR, ///< 2:CLK Line for YPBPR
FPLL_TUNE_CLK_LINE_FOR_VIDEO, ///< 3: CLK line for Video
FPLL_TUNE_CLK_LINE_FOR_DTV, ///< 4: CLK line for DTV
FPLL_TUNE_SNOW, ///< 5: SNOW
FPLL_TUNE_TYPEMASK = 0x7F, ///< 0x7F: tunning Type mask
FPLL_TUNE_INTERLACE = 0x80, ///< 0x80: interlace
} EnuFpllCtl;
//------------------------------------------------------------------------------
// ADC
//
typedef enum
{
MS_ADC_A_POWER_ON,
MS_ADC_B_POWER_ON,
MS_VDB_CVBS_POWER_ON,
MS_VDB_SV_POWER_ON,
MS_VDB_FBLANK_POWER_ON,
MS_VDA_CVBS_POWER_ON,
MS_VDA_SV_POWER_ON,
MS_VDA_FBLANK_POWER_ON,
MS_DVI_POWER_ON,
MS_ADC_VD_BLEND_POWER_ON,
MS_ADC_POWER_ALL_OFF,
} MS_ADC_POWER_ON_TYPE;
//------------------------------------------------------------------------------
///Input port type
typedef enum
{ // BK1_2F
INPUT_PORT_ADC_RGB, ///< 0: ADC RGB
INPUT_PORT_ADC_A_RGB, ///< 1: ADC_A RGB
INPUT_PORT_ADC_B_RGB, ///< 2: ADC_B RGB
INPUT_PORT_ADC_A_YPBPR, ///< 3: ADC_A YPBPR
INPUT_PORT_ADC_B_YPBPR, ///< 4: ADC_B YPBPR
INPUT_PORT_ADC_YPBPR, ///< 5: ADC YPBPR
#if(INPUT_YPBPR_VIDEO_COUNT==2)
INPUT_PORT_ADC_YPBPR2, ///< 6: ADC YPBPR2
#endif
#if ENABLE_DIGITAL_SOURCE// kevin 071213_0
INPUT_PORT_DIGITAL = INPUT_PORT_ADC_A_RGB,
#endif
#if ENABLE_INPUT_PIP1// kevin 071031_0
INPUT_PORT_PIP1 = INPUT_PORT_ADC_A_RGB,
#endif
#if ENABLE_INPUT_PIP2// kevin 071031_0
INPUT_PORT_PIP2 = INPUT_PORT_ADC_A_RGB,
#endif
INPUT_PORT_MS_CVBS0 = 0x0F, ///< 0x0F: MS CVBS0
INPUT_PORT_MS_CVBS1 = 0x1F, ///< 0x1F: MS CVBS1
INPUT_PORT_MS_CVBS2 =0x29, ///< 0x29: MS CVBS2
INPUT_PORT_MS_CVBS3 = 0x3F, ///< 0x3F: MS CVBS3
INPUT_PORT_MS_SV0 = 0x46, ///< 0x46: MS SV0
INPUT_PORT_MS_SV1 = 0x57, ///< 0x57: MS SV7
#if(ENABLE_SCART_VIDEO)
INPUT_PORT_AV_SCART0 = 0x49, ///< 0x49: AV SCART0
INPUT_PORT_AV_SCART1 = 0x28, ///< 0x28: AV SCART1
#endif
INPUT_PORT_MS_STORAGE = 0xFC, ///< 0xFC: external storage
INPUT_PORT_MS_CCIR656 = 0xFD, ///< 0xFE MS CCIR656
INPUT_PORT_MS_DTV = 0xFE, ///< 0xFE MS DTV
INPUT_PORT_NUMS, ///< Numbers of port type
INPUT_PORT_NONE = INPUT_PORT_NUMS,
} EN_INPUT_PORT_TYPE;
typedef enum
{
IP_ANALOG1 = 0x00,
IP_ANALOG2 = 0x01,
IP_ANALOG3 = 0x02,
IP_DVI = 0x03,
IP_VIDEO = 0x04,
IP_HDTV = 0x05,
IP_HDMI = 0x07,
} EN_ISELECT;
typedef enum
{ // BK0_04
MVD_CVBS = 0x00,
MVD_SVIDEO = 0x01,
MVD_YCBCR = 0x03,
MVD_RGB = 0x02,
MVD_CCIR656 = 0x10,
} EN_ISCTRL;
typedef enum
{
TV_SOUND_AUTO,
TV_SOUND_BG,
TV_SOUND_I,
TV_SOUND_DK,
TV_SOUND_L, // L
TV_SOUND_LL, // L'
TV_SOUND_M,
TV_SOUND_NUMS
}EN_TV_SOUND_SYSTEM;
typedef enum
{
CRT_SCAN_MODE_PROGRESS,
CRT_SCAN_MODE_75i,
CRT_SCAN_MODE_60i,
CRT_SCAN_MODE_DOUBLEi,
CRT_SCAN_MODE_NUMS
}EN_CRT_SCAN_MODE_TYPE;
typedef enum
{
/* general */
VIDEOSCREEN_MIN,
VIDEOSCREEN_NORMAL= VIDEOSCREEN_MIN,
VIDEOSCREEN_WIDE, ///< video full panel resolution
VIDEOSCREEN_ZOOM,
VIDEOSCREEN_CINEMA,
VIDEOSCREEN_ORIGIN,
/* specific options for wide panel */
VIDEOSCREEN_16by9_SUBTITLE,
#if(ENABLE_NON_LINEAR_SCALING)
VIDEOSCREEN_PANORAMA,
#endif
/* others */
VIDEOSCREEN_14by9, ///< 14:9
VIDEOSCREEN_ZOOM_130, ///< 130% scaling up
VIDEOSCREEN_ZOOM_108, ///< 108% scaling up
VIDEOSCREEN_NUMS, ///< numbers of video screen type
VIDEOSCREEN_16_9,
}EN_ASPECT_RATIO_TYPE;
// The order should be the same as enInputTypeOptionName in MApp_OSDString.h
/// INPUT SOURCE TYPE
typedef enum
{
INPUT_SOURCE_VGA, ///< PC - VGA
// kevin 071221 INPUT_SOURCE_TV, ///< VIDEO - TV Tuner 0
#if (INPUT_AV_VIDEO_COUNT == 1)
INPUT_SOURCE_CVBS, ///< VIDEO - CVBS 1
#elif (INPUT_AV_VIDEO_COUNT == 2)
INPUT_SOURCE_CVBS,
INPUT_SOURCE_CVBS2,
#endif
#if (INPUT_SV_VIDEO_COUNT == 1)
INPUT_SOURCE_SVIDEO, ///< VIDEO - SVideo 2
#elif (INPUT_SV_VIDEO_COUNT == 2)
INPUT_SOURCE_SVIDEO, ///< VIDEO - SVideo
INPUT_SOURCE_SVIDEO2, ///< VIDEO - SVideo
#endif
#if (INPUT_YPBPR_VIDEO_COUNT == 1)
INPUT_SOURCE_YPBPR, ///< VIDEO - YPbPr 3
#elif (INPUT_YPBPR_VIDEO_COUNT==2)
INPUT_SOURCE_YPBPR, ///< VIDEO - YPbPr 3
INPUT_SOURCE_YPBPR2, ///< VIDEO - YPbPr
#endif
#if ENABLE_DIGITAL_SOURCE// kevin 071213_0
INPUT_SOURCE_DIGITAL,
#endif
#if ENABLE_INPUT_PIP1// kevin 071031_0
INPUT_SOURCE_PIP1,
#endif
#if ENABLE_INPUT_PIP2// kevin 071031_0
INPUT_SOURCE_PIP2,
#endif
#if (INPUT_SCART_VIDEO_COUNT == 1)
INPUT_SOURCE_SCART, ///< VIDEO - SCART
#elif (INPUT_SCART_VIDEO_COUNT == 2)
INPUT_SOURCE_SCART,
INPUT_SOURCE_SCART2,
#endif
INPUT_SOURCE_VGA_PIP,
INPUT_SOURCE_VGA_PIP2,// kevin 071101_2
INPUT_SOURCE_NUM,
INPUT_SOURCE_NONE = INPUT_SOURCE_NUM,
} MS_INPUT_SOURCE_TYPE;
typedef enum
{
DATA_INPUT_SOURCE_MIN,
DATA_INPUT_SOURCE_DTV = DATA_INPUT_SOURCE_MIN,
DATA_INPUT_SOURCE_ATV,
#if (INPUT_AV_VIDEO_COUNT == 1)
DATA_INPUT_SOURCE_AV,
#elif (INPUT_AV_VIDEO_COUNT == 2)
DATA_INPUT_SOURCE_AV,
DATA_INPUT_SOURCE_AV2,
#endif
#if (INPUT_YPBPR_VIDEO_COUNT == 1)
DATA_INPUT_SOURCE_COMPONENT,
#elif (INPUT_YPBPR_VIDEO_COUNT == 2)
DATA_INPUT_SOURCE_COMPONENT,
DATA_INPUT_SOURCE_COMPONENT2,
#endif
DATA_INPUT_SOURCE_RGB,
DATA_INPUT_SOURCE_NUM,
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