📄 hwreg_s2.h
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#define ODD_GPO_SEL_3 0x309D //selec as GPO pin
#define ODD_GPO_DATA_0 0x309E // GPO data to pinout
#define ODD_GPO_DATA_1 0x309F // GPO data to pinout
#define ODD_GPO_DATA_2 0x30A0 // GPO data to pinout
#define ODD_GPO_DATA_3 0x30A1 // GPO data to pinout
#define ODD_GPO_OEZ_0 0x30A2 // 0:output, 1:input
#define ODD_GPO_OEZ_1 0x30A3
#define ODD_GPO_OEZ_2 0x30A4
#define ODD_GPO_OEZ_3 0x30A5
#define ODD_GPI_0 0x30AA // ODD is gPi pin
#define ODD_GPI_1 0x30AB
#define ODD_GPI_2 0x30AC
#define ODD_GPI_3 0x30AD
#define MCUCLK_SEL 0x1003
// MIIC control:
#define IIC0_CTRL 0x3420
#define IIC0_CLK_SEL 0x3422
#define IIC0_WDATA 0x3424
#define IIC0_RDATA 0x3426
#define IIC0_STATUS 0x3428
#define ISP_WR_HEAD 0x1060
#define ISP_WR_AH 0x1061
#define ISP_WR_AM 0x1062
#define ISP_WR_AL 0x1063
#define ISP_WR_DATA 0x1064
#define ISP_CTRL 0x1065
#define ISP_RD_DATA 0x1066
#define ISP_CEB 0x1067
#define ISP_OEB 0x1068
#define ISP_WEB 0x1069
#define ISP_CMDLEN 0x106A
#define ISP_CTRL1 0x106B
//------------------------------------------------------------------------------
// IR register define
//------------------------------------------------------------------------------
#define IR_ENABLE 0x34A4 //add by Jason071031
#define IR_CTRL 0x3D80
#define IR_CHECK 0x3D81
#define IR_HDC_UPB_L 0x3D82
#define IR_HDC_UPB_H 0x3D83
#define IR_HDC_LOB_L 0x3D84
#define IR_HDC_LOB_H 0x3D85
#define IR_OFC_UPB_L 0x3D86
#define IR_OFC_UPB_H 0x3D87
#define IR_OFC_LOB_L 0x3D88
#define IR_OFC_LOB_H 0x3D89
#define IR_OFC_RP_UPB_L 0x3D8A
#define IR_OFC_RP_UPB_H 0x3D8B
#define IR_OFC_RP_LOB_L 0x3D8C
#define IR_OFC_RP_LOB_H 0x3D8D
#define IR_LG01H_UPB_L 0x3D8E
#define IR_LG01H_UPB_H 0x3D8F
#define IR_LG01H_LOB_L 0x3D90
#define IR_LG01H_LOB_H 0x3D91
#define IR_LG0_UPB_L 0x3D92
#define IR_LG0_UPB_H 0x3D93
#define IR_LG0_LOB_L 0x3D94
#define IR_LG0_LOB_H 0x3D95
#define IR_LG1_UPB_L 0x3D96
#define IR_LG1_UPB_H 0x3D97
#define IR_LG1_LOB_L 0x3D98
#define IR_LG1_LOB_H 0x3D99
#define IR_SEPR_UPB_L 0x3D9A
#define IR_SEPR_UPB_H 0x3D9B
#define IR_SEPR_LOB_L 0x3D9C
#define IR_SEPR_LOB_H 0x3D9D
#define IR_TIMEOUT_CYC_0 0x3D9E
#define IR_TIMEOUT_CYC_1 0x3D9F
#define IR_TIMEOUT_CYC_2 0x3DA0
#define IR_CODEBYTE 0x3DA1
#define IR_SEPR_BIT 0x3DA2
#define IR_FIFO_CTRL 0x3DA3 // different location with Saturn
#define IR_CCODE_L 0x3DA4
#define IR_CCODE_H 0x3DA5
#define IR_GLHRM_NUM_L 0x3DA6
#define IR_GLHRM_NUM_H 0x3DA7
#define IR_CKDIV_NUM_REG 0x3DA8 // different location with Saturn
#define IR_KEY 0x3DA9
#define IR_SHOT_CNT_0 0x3DAA
#define IR_SHOT_CNT_1 0x3DAB
#define IR_SHOT_CNT_2 0x3DAC
#define IR_RPT_FIFOEMPTY 0x3DAD
#define IR_FIFO_READ_PULSE 0x3DB0 // added in Saturn2
#define TAG_A0 0x10A8
#define TAG_A1 0x10A9
#define TAG_A2 0x10AA
#define TAG_A3 0x10AB
#define TAG_B0 0x10AC
#define TAG_B1 0x10AD
#define TAG_B2 0x10AE
#define TAG_B3 0x10AF
#define VDMCU_MIU_MAP_CMD 0x10C0
#define VDMCU_SDRAM_CODE_MAP 0x10C1
#define VDMCU_SDRAM_CODE_MAP_H 0x10C2
#define VDMCU_CACHE_ACCESS 0x10C6
#define VDMCU_CACHE_HIT 0x10C7
#define VDMCU_TAG_A0 0x10C8
#define VDMCU_TAG_A1 0x10C9
#define VDMCU_TAG_A2 0x10CA
#define VDMCU_TAG_A3 0x10CB
#define VDMCU_TAG_B0 0x10CC
#define VDMCU_TAG_B1 0x10CD
#define VDMCU_TAG_B2 0x10CE
#define VDMCU_TAG_B3 0x10CF
#define PM_PD 0x10D0
#define PM_TH0 0x10D1
#define PM_TH1 0x10D2
#define PM_XTL_PWD0 0x10D3
#define PM_XTL_PWD1 0x10D4
#define PM_SB_PWD0 0x10D5
#define PM_SB_PWD1 0x10D6
#define PM_OFF_FLAG (0x3C1E) // U02(0x3C1C) /U030x3C1E)
#define PM_SYS_PD (0x01)
#define PM_GPIO_ACT_LEVEL (0x02)
#define PM_IR_ACT_LEVEL (0x04)
#define PM_IR_PD (0x08)
#define PM_TEST_MODE (0x10)
#define PM_CHK_IR_NOISE (0x20)
#define PM_XTL_PWD0_VAL (0x8E)
#define PM_XTL_PWD1_VAL (0x9F)
#define PM_SB_PWD0_VAL (0xB4)
#define PM_SB_PWD1_VAL (0xA5)
#define PM_TH0_VAL (0xBA)
#define PM_TH1_VAL (0x0D)
#define PM_FIRST_BOOTUP (0x01)
#define PM_MODE_MASK (0x06)
#if ( 1 ) //POWERUP_MODE == PUMODE_WORK )
#define PM_MODE_ON (0x00)
#define PM_MODE_OFF_EXEC (0x02)
#define PM_MODE_OFF (0x04)
#define PM_MODE_ON_EXEC (0x06)
#else
#define PM_MODE_ON (0x02)
#define PM_MODE_OFF_EXEC (0x00)
#define PM_MODE_OFF (0x04)
#define PM_MODE_ON_EXEC (0x06)
#endif
#define PM_P3_RESET_FLAG (0x08)
#define PM_PDMODE_MASK (0x30)
#define PM_PDMODE_S1 (0x00)
#define PM_PDMODE_S2 (0x10)
#define PM_PDMODE_S3 (0x20)
#define PM_PDMODE_S4 (0x30)
#define VGA_POWERSAVING (0x40)
//------------------------------------------------------------------------------
// 2. - MIU Reg
//------------------------------------------------------------------------------
#define DDR_FREQ_SET_0 0x1220
#define DDR_FREQ_SET_1 0x1221
#define DDR_FREQ_STEP 0x1224
#define DDR_FREQ_DIV_1 0x1225
#define DDR_FREQ_INPUT_DIV_2 0x1226
#define DDR_FREQ_LOOP_DIV_2 0x1227
#define DDR_CLK_SELECT 0x123E
#define DDR_FREQ_STATUS 0x123F
#define MIU_PROTECT0_EN 0x12C0
#define MIU_PROTECT0_ID 0x12C1
#define MIU_PROTECT0_START_ADDR_H 0x12C2
#define MIU_PROTECT0_START_ADDR_L 0x12C3
#define MIU_PROTECT0_END_ADDR_H 0x12C4
#define MIU_PROTECT0_END_ADDR_L 0x12C5
#define MIU_DDFSET 0x1220
#define MIU_DDFSPAN 0x1222
#define MIU_DDFSTEP 0x1224
#define MIU_PLLCTRL 0x1225
#define MIU_RQ1_CTRL0 0x1260
// MIU self test (BIST)
#define REG_MIU_TEST_MODE 0x12E0
#define REG_MIU_TEST_BASE 0x12E2
#define REG_MIU_TEST_LENGTH 0x12E4
#define REG_MIU_TEST_DATA 0x12E8
//---------------------------------------------------
//MIU_PROTECT0_ID
#define MCU_WRITE_ID 0x05
#define MCU_READ_ID 0x06
#define MAD_WRITE_ID 0x08
//----------------------------------------------------------------------------
// 5. DEMUX Reg
//----------------------------------------------------------------------------
#define NIM_HWCONFIG0 0x1558
#define NIM_HWCONFIG1 0x155A
#define NIM_HWCONFIG2 0x1584
#define NIM_HWCONFIG3 0x1586
#define NIM_HWINPORT 0x155E
#define PCR_L0 0x1560
#define PCR_L1 0x1561
#define PCR_L2 0x1562
#define PCR_L3 0x1563
#define PCR_H 0x1564
#define SECISR_INTCODE0 0x1570
#define SECISR_INTCODE1 0x1571
#define SECISR_INTCODE2 0x1572
#define SECISR_INTCODE3 0x1573
#define SECISR_ACKCODE0 0x1580
#define SECISR_ACKCODE1 0x1581
#define SECISR_ACKCODE2 0x1582
#define SECISR_ACKCODE3 0x1583
#define TSP_DMA_RADDR0 0x15F0
#define TSP_DMA_RADDR1 0x15F1
#define TSP_DMA_RNUM0 0x15F2
#define TSP_DMA_RNUM1 0x15F3
#define TSP_CTRL 0x15F4
//----------------------------------------------------------------------------
// 11. GOP Reg
//----------------------------------------------------------------------------
#define GOP_REG_VAL(x) (1<<x)
#define __GOP_REG(reg) ((reg) * 2)
#define GOP_GWIN_EN __GOP_REG(0x00)
#define GOP_GWIN_DTYPE __GOP_REG(0x01)
#define GOP_BLINK __GOP_REG(0x02)
#define GOP_ROLL __GOP_REG(0x03)
#define GOP_GWIN_ALPHA01 __GOP_REG(0x04)
#define GOP_GWIN_ALPHA23 __GOP_REG(0x05)
#define GOP_PDATA __GOP_REG(0x06)
#define GOP_PDATA_ADR __GOP_REG(0x07)
#define GOP_PDATA_WR __GOP_REG(0x08)
#define GOP_PSHIFT __GOP_REG(0x09)
#define GOP_SVM __GOP_REG(0x0A)
#define GOP_GWIN_PINPON_POS (0x04)
#define GOP_GWIN_PINPON_VAL GOP_REG_VAL(GOP_GWIN_PINPON_POS)
#define GOP_GWIN_AVG0_EN_POS (0x05)
#define GOP_GWIN_AVG0_EN_VAL GOP_REG_VAL(GOP_GWIN_AVG0_EN_POS)
#define GOP_GWIN_AVG1_EN_POS (0x06)
#define GOP_GWIN_AVG1_EN_VAL GOP_REG_VAL(GOP_GWIN_AVG1_EN_POS)
#define GOP_GWIN_TWIN_EN_POS (0x09)
#define GOP_GWIN_TWIN_EN_VAL GOP_REG_VAL(GOP_GWIN_TWIN_EN_POS)
#define GOP_MIU_RD_TSH __GOP_REG(0x0B)
#define GOP_T⌨️ 快捷键说明
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