hwreg_s2.h

mstar 776 开发的车载dvd

#define DAC_CLK_VD                              0x04
#define DAC_CLK_XTAL                            0x0C

//---------------------------------------------
// definition for REG_CKG_FCLK  //reg[0x1e35]
#define FCLK_CLK_ENABLE                         0x00
#define FCLK_CLK_DISABLE                        0x01
#define FCLK_CLK_NONINVERT                      0x00
#define FCLK_CLK_INVERT                         0x02
#define FCLK_CLK_MASK                           0x3C
#define FCLK_CLK_MPLL                           0x00
#define FCLK_CLK_MIU                            0x04
#define FCLK_CLK_ODCLK                          0x08
#define FCLK_CLK_IDCLK1                         0x0C    // S3+ only
#define FCLK_CLK_IDCLK2                         0x10
#define FCLK_CLK_0_1                            0x14
#define FCLK_CLK_0_2                            0x18
#define FCLK_CLK_XTAL_0                         0x1C
#define FCLK_CLK_XTAL_1                         0x20
//---------------------------------------------
// definition for REG_CKG_FMCLK //reg[0x1e36]
#define FMCLK_CLK_ENABLE                        0x00
#define FMCLK_CLK_DISABLE                       0x01
#define FMCLK_CLK_NONINVERT                     0x00
#define FMCLK_CLK_INVERT                        0x02
#define FMCLK_CLK_MASK                          0x3C
#define FMCLK_CLK_MIU                           0x00
#define FMCLK_CLK_MPLL                          0x04
#define FMCLK_CLK_ODCLK                         0x08
#define FMCLK_CLK_IDCLK1                        0x0C
#define FMCLK_CLK_IDCLK2                        0x10
#define FMCLK_CLK_0_1                           0x14
#define FMCLK_CLK_0_2                           0x18
#define FMCLK_CLK_0_3                           0x1C
#define FMCLK_CLK_DFT                           0x20

//---------------------------------------------
// definition for REG_CKG_ODCLK //reg[0x1e37]
#define ODCLK_CLK_ENABLE                        0x00
#define ODCLK_CLK_DISABLE                       0x01
#define ODCLK_CLK_NONINVERT                     0x00
#define ODCLK_CLK_INVERT                        0x02
#define ODCLK_CLK_MASK                          0x3C
#define ODCLK_CLK_ADC                           0x00
#define ODCLK_CLK_VD                            0x08
#define ODCLK_CLK_1                             0x10
#define ODCLK_CLK_EX_DI                         0x14
#define ODCLK_CLK_XTAL_0                        0x18
#define ODCLK_CLK_LPLL                          0x1C
#define ODCLK_CLK_XTAL_1                        0x20

//---------------------------------------------
// definition for REG_CKG_VEIN  //reg[0x1e38]
#define VEIN_CLK_ENABLE                         0x00
#define VEIN_CLK_DISABLE                        0x01
#define VEIN_CLK_NONINVERT                      0x00
#define VEIN_CLK_INVERT                         0x02
#define VEIN_CLK_MASK                           0x3C
#define VEIN_CLK_ADC                            0x00
#define VEIN_CLK_DVI                            0x04
#define VEIN_CLK_VD                             0x08
#define VEIN_CLK_MPEG0                          0x0C
#define VEIN_CLK_1                              0x10
#define VEIN_CLK_EX_DI                          0x14
#define VEIN_CLK_0_0                            0x18
#define VEIN_CLK_0_1                            0x1C
#define VEIN_CLK_DFT                            0x20

//---------------------------------------------
// definition for REG_CKG_FCIE  //reg[0x1e39]
#define FCIE_CLK_ENABLE                         0x00
#define FCIE_CLK_DISABLE                        0x01
#define FCIE_CLK_NONINVERT                      0x00
#define FCIE_CLK_INVERT                         0x02
#define FCIE_CLK_MASK                           0x7C
#define FCIE_CLK_86D256                         0x00
#define FCIE_CLK_86D64                          0x04
#define FCIE_CLK_86D16                          0x08
#define FCIE_CLK_54D4                           0x0C
#define FCIE_CLK_72D4                           0x10
#define FCIE_CLK_86D4                           0x14
#define FCIE_CLK_54D2                           0x18
#define FCIE_CLK_72D2                           0x1C
#define FCIE_CLK_86D2                           0x20
#define FCIE_CLK_54MHZ                          0x24
#define FCIE_CLK_72MHZ                          0x28
#define FCIE_CLK_0_0                            0x2C
#define FCIE_CLK_0_1                            0x30
#define FCIE_CLK_0_2                            0x34
#define FCIE_CLK_0_3                            0x38
#define FCIE_CLK_0_4                            0x3C
#define FCIE_CLK_XTAL                           0x40

//---------------------------------------------
// definition for REG_CKG_TS    //reg[0x1e3a]
#define TS2_CLK_ENABLE                          0x00
#define TS2_CLK_DISABLE                         0x01
#define TS2_CLK_NONINVERT                       0x00
#define TS2_CLK_INVERT                          0x02
#define TS2_CLK_MASK                            0x0C
#define TS2_CLK_TS2                             0x00
#define TS2_CLK_0_0                             0x04
#define TS2_CLK_0_1                             0x08
#define TS2_CLK_XTAL                            0x0C
//----------------------------------
#define TSOUT_CLK_ENABLE                        0x00
#define TSOUT_CLK_DISABLE                       0x10
#define TSOUT_CLK_NONINVERT                     0x00
#define TSOUT_CLK_INVERT                        0x20
#define TSOUT_CLK_MASK                          0xC0
#define TSOUT_CLK_27MHZ                         0x00
#define TSOUT_CLK_36MHZ                         0x40
#define TSOUT_CLK_43MHZ                         0x80
#define TSOUT_CLK_XTAL                          0xC0

//---------------------------------------------
// definition for REG_CKG_IDCLK1  //reg[0x1e3e]
#define IDCLK1_CLK_ENABLE                       0x00
#define IDCLK1_CLK_DISABLE                      0x01
#define IDCLK1_CLK_NONINVERT                    0x00
#define IDCLK1_CLK_INVERT                       0x02
#define IDCLK1_CLK_MASK                         0x3C
#define IDCLK1_CLK_ADC                          0x00
//#define IDCLK1_CLK_DVI                          0x04
#define IDCLK1_CLK_VD                           0x08
#define IDCLK1_CLK_DC0                          0x0C
#define IDCLK1_CLK_VD20                        0x10
#define IDCLK1_CLK_EX_DI                        0x14
#define IDCLK1_CLK_VDADC                        0x18
#define IDCLK1_CLK_0                            0x1C
#define IDCLK1_CLK_XTAL                         0x20

//---------------------------------------------
// definition for REG_CKG_IDCLK2  //reg[0x1e3f]
#define IDCLK2_CLK_ENABLE                       0x00
#define IDCLK2_CLK_DISABLE                      0x01
#define IDCLK2_CLK_NONINVERT                    0x00
#define IDCLK2_CLK_INVERT                       0x02
#define IDCLK2_CLK_MASK                         0x3C
#define IDCLK2_CLK_ADC                          0x00
//#define IDCLK2_CLK_DVI                          0x04
#define IDCLK2_CLK_VD                           0x08
#define IDCLK2_CLK_DC0                          0x0C
#define IDCLK2_CLK_VD20                        0x10
#define IDCLK2_CLK_EX_DI                        0x14
#define IDCLK2_CLK_VDADC                        0x18
#define IDCLK2_CLK_0                            0x1C
#define IDCLK2_CLK_XTAL                         0x20
//---------------------------------------------
// definition for REG_CKG_STRLD //reg[0x1e44]
#define STRLD_CLK_ENABLE                        0x00
#define STRLD_CLK_DISABLE                       0x01
#define STRLD_CLK_NONINVERT                     0x00
#define STRLD_CLK_INVERT                        0x02
#define STRLD_CLK_MASK                          0x0C
#define STRLD_CLK_144MHZ                        0x00
#define STRLD_CLK_123MHZ                        0x04
#define STRLD_CLK_108MHZ                        0x08
#define STRLD_CLK_XTAL                          0x0C

//---------------------------------------------
// definition for REG_CKG_MCU   //reg[0x1e45]
// MPLL   = XTAL * 36
// USBCLK = XTAL * 40
#define MCU_CLK_ENABLE                          0x00
#define MCU_CLK_DISABLE                         0x01
#define MCU_CLK_NONINVERT                       0x00
#define MCU_CLK_INVERT                          0x02
#define MCU_CLK_MASK                            0x1C

#define MCU_CLK_54MHZ    0
#define MCU_CLK_144MHZ   _BIT2
#define MCU_CLK_123MHZ   _BIT3
#define MCU_CLK_108MHZ   (_BIT2+_BIT3)
#define MCU_CLK_86MHZ    _BIT4
#define MCU_CLK_MEM      (_BIT4+_BIT2)
#define MCU_CLK_MEMD2    (_BIT4+_BIT3)
#define MCU_CLK_36kHz    (_BIT4+_BIT3+_BIT2)

//---------------------------------------------------------
//#define SPI_CLK_ENABLE                          0x00
//#define SPI_CLK_DISABLE                         0x01
//#define SPI_CLK_NONINVERT                       0x00
//#define SPI_CLK_INVERT                          0x02
#define SPI_CLK_MASK                            0x1C

#define SPI_CLK_XTAL                            0
#define SPI_CLK_27MHZ                           _BIT2
#define SPI_CLK_36MHZ                           _BIT3
#define SPI_CLK_43MHZ                           (_BIT2+_BIT3)
#define SPI_CLK_54MHZ                           _BIT4
#define SPI_CLK_72MHZ                           (_BIT4+_BIT2)
#define SPI_CLK_86MHZ                           (_BIT4+_BIT3)
#define SPI_CLK_108MHZ                          (_BIT4+_BIT3+_BIT2)

//---------------------------------------------
// definition for REG_CKG_DHC0  //reg[0x1e58]
#define DHCDDR_CLK_NONGATE                      0x00
#define DHCDDR_CLK_GATING                       0x01
#define DHCDDR_CLK_NONINVERT                    0x00
#define DHCDDR_CLK_INVERT                       0x02
#define DHCSYNTH_CLK_NONGATE                    0x00
#define DHCSYNTH_CLK_GATING                     0x04
#define DHCSYNTH_CLK_NONINVERT                  0x00
#define DHCSYNTH_CLK_INVERT                     0x08
#define DHCSYNTH_CLK_MASK                       0x30
#define DHCSYNTH_CLK_D2                         0x00
#define DHCSYNTH_CLK_D2P5                       0x10
#define DHCSYNTH_CLK_D3                         0x20
#define DHCSYNTH_CLK_D4                         0x30

//---------------------------------------------
// definition for REG_CKG_DHC1  //reg[0x1e59]
#define DHCMCU_CLK_NONGATE                      0x00
#define DHCMCU_CLK_GATING                       0x01
#define DHCMCU_CLK_NONINVERT                    0x00
#define DHCMCU_CLK_INVERT                       0x02
#define DHCMCU_CLK_MASK                         0x3C
#define DHCMCU_CLK_43MHZ                        0x00
#define DHCMCU_CLK_54MHZ                        0x04
#define DHCMCU_CLK_62MHZ                        0x08
#define DHCMCU_CLK_72MHZ                        0x0C
#define DHCMCU_CLK_86MHZ                        0x10
#define DHCMCU_CLK_108MHZ                       0x14
#define DHCMCU_CLK_RESERVED                     0x18
#define DHCLIVE_CLK_NONGATE                     0x00
#define DHCLIVE_CLK_GATING                      0x40
#define DHCLIVE_CLK_NONINVERT                   0x00
#define DHCLIVE_CLK_INVERT                      0x80

//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
//PWM setting group PWM_REG_BASE
#define PWM0_PWM1_CTRL                          0x3460
#define PWM0_PERIOD_LOW                         0x3462
#define PWM0_PERIOD_HIGH                        0x3463
#define PWM1_PERIOD_LOW                         0x3464
#define PWM1_PERIOD_HIGH                        0x3465
#define PWM0_PERIOD_DUTY                        0x3466
#define PWM1_PERIOD_DUTY                        0x3467

#define PWM2_PWM3_CTRL                          0x3468
#define PWM2_POLARITY                           0x3469
#define PWM2_PERIOD_LOW                         0x346A
#define PWM2_PERIOD_HIGH                        0x346B
#define PWM3_PERIOD_LOW                         0x346C
#define PWM3_PERIOD_HIGH                        0x346D
#define PWM2_PERIOD_DUTY                        0x346E
#define PWM3_PERIOD_DUTY                        0x346F

#define PWM5_TRIG                               0x3470
#define PWM6_TRIG                               0x3472

//-------------------------------------------
//SC2_REG_BASE  //0x3000
#define REG_SEL_CLOCK                           0x3081
#define REG_SEL_GPO_0                           0x3086
#define REG_SEL_GPO_1                           0x3087

#define REG_SEL_TTL_0                           0x3088
#define REG_SEL_TTL_1                           0x3089

#define ODD_IS_GPIO_0                           0x308C
#define ODD_IS_GPIO_1                           0x308D
#define ODD_IS_GPIO_2                           0x308E
#define ODD_IS_GPIO_3                           0x308F  //VS,HS,DE,CLK,b0~b7,g0~g7,r0~r7

#define ODD_GPO_SEL_0                           0x309A  //selec as GPO pin ;switch to outpur pad
#define ODD_GPO_SEL_1                           0x309B  //selec as GPO pin
#define ODD_GPO_SEL_2                           0x309C  //selec as GPO pin