📄 hwreg_s2.h
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// Clock generate setting
//---------------------------------------------
// definition for REG_CKG_USBRIU //reg[0x1e24]
#define USB_CLK_ENABLE 0x00
#define USB_CLK_DISABLE 0x01
#define USB_CLK_NONINVERT 0x00
#define USB_CLK_INVERT 0x02
//---------------------------------------------
// definition for REG_CKG_MIU //reg[0x1e25]
#define MIU_CLK_ENABLE 0x00
#define MIU_CLK_DISABLE 0x10
#define MIU_CLK_NONINVERT 0x00
#define MIU_CLK_INVERT 0x20
#define MIU_CLK_MASK 0xC0
#define MIU_CLK_108MHZ 0x00
#define MIU_CLK_100MHZ 0x40
#define MIU_CLK_143MHZ 0x80
#define MIU_CLK_123MHZ 0xC0
//---------------------------------------------
// definition for REG_CKG_TCK //reg[0x1e26]
#define TCK_CLK_ENABLE 0x00
#define TCK_CLK_DISABLE 0x10
#define TCK_CLK_NONINVERT 0x00
#define TCK_CLK_INVERT 0x20
//----------------------------------
#define AEON_CLK_ENABLE 0x00
#define AEON_CLK_DISABLE 0x40
#define AEON_CLK_NONINVERT 0x00
#define AEON_CLK_INVERT 0x80
//---------------------------------------------
// definition for REG_CKG_STC0TSP //reg[0x1e27]
#define TSP_CLK_ENABLE 0x00
#define TSP_CLK_DISABLE 0x01
#define TSP_CLK_NONINVERT 0x00
#define TSP_CLK_INVERT 0x02
#define TSP_CLK_MASK 0x0C
#define TSP_CLK_144MHZ 0x00
#define TSP_CLK_123MHZ 0x04
#define TSP_CLK_72MHZ 0x08
#define TSP_CLK_XTAL 0x0C
//----------------------------------
#define STC0_CLK_ENABLE 0x00
#define STC0_CLK_DISABLE 0x10
#define STC0_CLK_NONINVERT 0x00
#define STC0_CLK_INVERT 0x20
#define STC0_CLK_MASK 0xC0
#define STC0_CLK_STC0 0x00
#define STC0_CLK_1 0x40
#define STC0_CLK_27MHZ 0x80
#define STC0_CLK_XTAL 0xC0
//---------------------------------------------
// definition for REG_CKG_MADSTC //reg[0x1e28]
#define MADSTC_CLK_ENABLE 0x00
#define MADSTC_CLK_DISABLE 0x10
#define MADSTC_CLK_NONINVERT 0x00
#define MADSTC_CLK_INVERT 0x20
#define MADSTC_CLK_MASK 0xC0
#define MADSTC_CLK_STC0 0x00
#define MADSTC_CLK_1 0x40
#define MADSTC_CLK_27MHZ 0x80
#define MADSTC_CLK_XTAL 0xC0
//---------------------------------------------
// definition for REG_CKG_MVD //reg[0x1e29]
#define MVDBOOT_CLK_ENABLE 0x00
#define MVDBOOT_CLK_DISABLE 0x01
#define MVDBOOT_CLK_NONINVERT 0x00
#define MVDBOOT_CLK_INVERT 0x02
#define MVDBOOT_CLK_MASK 0x0C
#define MVDBOOT_CLK_144MHZ 0x00
#define MVDBOOT_CLK_123MHZ 0x04
#define MVDBOOT_CLK_MIU 0x08
#define MVDBOOT_CLK_XTAL 0x0C
//----------------------------------
#define MVD_CLK_ENABLE 0x00
#define MVD_CLK_DISABLE 0x10
#define MVD_CLK_NONINVERT 0x00
#define MVD_CLK_INVERT 0x20
#define MVD_CLK_144MHZ 0x00
#define MVD_CLK_123MHZ 0x40
#define MVD_CLK_MIU 0x80
#define MVD_CLK_XTAL 0xC0
//---------------------------------------------
// definition for REG_CKG_DC0M4V //reg[0x1e2a]
#define M4VD_CLK_ENABLE 0x00
#define M4VD_CLK_DISABLE 0x01
#define M4VD_CLK_NONINVERT 0x00
#define M4VD_CLK_INVERT 0x02
#define M4VD_CLK_MASK 0x0C
#define M4VD_CLK_144MHZ 0x00
#define M4VD_CLK_123MHZ 0x04
#define M4VD_CLK_108MHZ 0x08
#define M4VD_CLK_XTAL 0x0C
//----------------------------------
#define DC0_CLK_ENABLE 0x00
#define DC0_CLK_DISABLE 0x10
#define DC0_CLK_NONINVERT 0x00
#define DC0_CLK_INVERT 0x20
#define DC0_CLK_MASK 0xC0
#define DC0_CLK_SYNC 0x00
#define DC0_CLK_FREERUN 0x40
#define DC0_CLK_27MHZ 0x80
#define DC0_CLK_XTAL 0xC0
//---------------------------------------------
// definition for REG_CKG_GE //reg[0x1e2b]
#define GE_CLK_ENABLE 0x00
#define GE_CLK_DISABLE 0x10
#define GE_CLK_NONINVERT 0x00
#define GE_CLK_INVERT 0x20
#define GE_CLK_MASK 0xC0
#define GE_CLK_123MHZ 0x00
#define GE_CLK_108MHZ 0x40
#define GE_CLK_86MHZ 0x80
#define GE_CLK_72MHZ 0xC0
//---------------------------------------------
// definition for REG_CKG_GOP //reg[0x1e2c]
#define GOP0_CLK_ENABLE 0x00
#define GOP0_CLK_DISABLE 0x01
#define GOP0_CLK_NONINVERT 0x00
#define GOP0_CLK_INVERT 0x02
#define GOP0_CLK_MASK 0x0C
#define GOP0_CLK_ODCLK 0x00
#define GOP0_CLK_IDCLK2 0x04
#define GOP0_CLK_IDCLK1 0x08
#define GOP0_CLK_XTAL 0x0C
//----------------------------------
#define GOP1_CLK_ENABLE 0x00
#define GOP1_CLK_DISABLE 0x10
#define GOP1_CLK_NONINVERT 0x00
#define GOP1_CLK_INVERT 0x20
#define GOP1_CLK_MASK 0xC0
#define GOP1_CLK_ODCLK 0x00
#define GOP1_CLK_IDCLK2 0x40
#define GOP1_CLK_IDCLK1 0x80
#define GOP1_CLK_XTAL 0xC0
//---------------------------------------------
// definition for REG_CKG_VD //reg[0x1e2d]
#define VD_CLK_ENABLE 0x00
#define VD_CLK_DISABLE 0x10
#define VD_CLK_NONINVERT 0x00
#define VD_CLK_INVERT 0x20
#define VD_CLK_MASK 0xC0
#define VD_CLK_VD 0x00
#define VD_CLK_0 0x40
#define VD_CLK_TESTMODE 0x80
#define VD_CLK_XTAL 0xC0
//---------------------------------------------
// definition for REG_CKG_VDS //reg[0x1e2e]
#define VDMCU_CLK_ENABLE 0x00
#define VDMCU_CLK_DISABLE 0x01
#define VDMCU_CLK_NONINVERT 0x00
#define VDMCU_CLK_INVERT 0x02
#define VDMCU_CLK_MASK 0x0C
#define VDMCU_CLK_54MHZ 0x00
#define VDMCU_CLK_61MHZ _BIT2
#define VDMCU_CLK_30MHZ _BIT3
#define VDMCU_CLK_108MHZ (_BIT2+_BIT3)
// related to reg[0x1e98]
#define VDMCU_CLK_86MHZ 0x00
#define VDMCU_CLK_MEM _BIT2
#define VDMCU_CLK_MEMDIV2 _BIT3
#define VDMCU_CLK_36MHZ (_BIT2+_BIT3)
//----------------------------------
#define VD200_CLK_ENABLE 0x00
#define VD200_CLK_DISABLE 0x10
#define VD200_CLK_NONINVERT 0x00
#define VD200_CLK_INVERT 0x20
#define VD200_CLK_MASK 0xC0
#define VD200_CLK_216MHZ 0x00
#define VD200_CLK_0MHZ0 0x40
#define VD200_CLK_0MHZ1 0x80
#define VD200_CLK_XTAL 0xC0
//---------------------------------------------
// definition for REG_CKG_HDC //reg[0x1e2f]
#define HDC_CLK_ENABLE 0x00
#define HDC_CLK_DISABLE 0x01
#define HDC_CLK_NONINVERT 0x00
#define HDC_CLK_INVERT 0x02
#define HDC_CLK_MASK 0x3C
#define HDC_CLK_12MHZ 0x00
#define HDC_CLK_54MHZ 0x04
#define HDC_CLK_62MHZ 0x08
#define HDC_CLK_72MHZ 0x0C
#define HDC_CLK_86MHZ 0x10
#define HDC_CLK_108MHZ 0x14
#define HDC_CLK_0_0 0x18
#define HDC_CLK_0_1 0x1C
#define HDC_CLK_XTAL 0x20
//---------------------------------------------
// definition for REG_CKG_FICLK //reg[0x1e30]
#define FICLKF2_CLK_ENABLE 0x00
#define FICLKF2_CLK_DISABLE 0x10
#define FICLKF2_CLK_NONINVERT 0x00
#define FICLKF2_CLK_INVERT 0x20
#define FICLKF2_CLK_MASK 0xC0
#define FICLKF2_CLK_IDCLK2 0x00
#define FICLKF2_CLK_FCLK 0x40
#define FICLKF2_CLK_IDCLK1 0x80
#define FICLKF2_CLK_XTAL 0xC0
#define FICLKF1_CLK_ENABLE 0x00
#define FICLKF1_CLK_DISABLE 0x01
#define FICLKF1_CLK_NONINVERT 0x00
#define FICLKF1_CLK_INVERT 0x02
#define FICLKF1_CLK_MASK 0x0C
#define FICLKF1_CLK_IDCLK2 0x00
#define FICLKF1_CLK_FCLK 0x04
#define FICLKF1_CLK_IDCLK1 0x08
#define FICLKF1_CLK_XTAL 0x0C
//---------------------------------------------
// definition for REG_CKG_PCM //reg[0x1e31]
#define PCM_CLK_ENABLE 0x00
#define PCM_CLK_DISABLE 0x10
#define PCM_CLK_NONINVERT 0x00
#define PCM_CLK_INVERT 0x20
#define PCM_CLK_MASK 0xC0
#define PCM_CLK_27MHZ_0 0x00
#define PCM_CLK_27MHZ_1 0x40
#define PCM_CLK_XTAL_0 0x80
#define PCM_CLK_XTAL_1 0xC0
//---------------------------------------------
// definition for REG_CKG_VE //reg[0x1e33]
#define VE_CLK_ENABLE 0x00
#define VE_CLK_DISABLE 0x01
#define VE_CLK_NONINVERT 0x00
#define VE_CLK_INVERT 0x02
#define VE_CLK_MASK 0x0C
#define VE_CLK_27MHZ_0 0x00
#define VE_CLK_27MHZ_1 0x04
#define VE_CLK_XTAL_0 0x08
#define VE_CLK_XTAL_1 0x0C
//----------------------------------
#define VDDAC_CLK_ENABLE 0x00
#define VDDAC_CLK_DISABLE 0x10
#define VDDAC_CLK_NONINVERT 0x00
#define VDDAC_CLK_INVERT 0x20
#define VDDAC_CLK_MASK 0xC0
#define VDDAC_CLK_27MHZ 0x00
#define VDDAC_CLK_54MHZ 0x40
#define VDDAC_CLK_108MHZ 0x80
#define VDDAC_CLK_DFT 0xC0
//---------------------------------------------
// definition for REG_CKG_SDRDAC //reg[0x1e34]
#define DAC_CLK_ENABLE 0x00
#define DAC_CLK_DISABLE 0x01
#define DAC_CLK_NONINVERT 0x00
#define DAC_CLK_INVERT 0x02
#define DAC_CLK_MASK 0x0C
#define DAC_CLK_ODCLK 0x00
#define DAC_CLK_0 0x08
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