hwreg_s2.h

mstar 776 开发的车载dvd

#define REG_CT_MISC1                            0x1E23
#define REG_CKG_USBRIU                          0x1E24
#define REG_CKG_MIU                             0x1E25
#define REG_CKG_TCK                             0x1E26
#define REG_CKG_STC0TSP                         0x1E27
#define REG_CKG_MADSTC                          0x1E28
#define REG_CKG_MVD                             0x1E29
#define REG_CKG_DC0M4V                          0x1E2A
#define REG_CKG_GE                              0x1E2B
#define REG_CKG_GOP                             0x1E2C
#define REG_CKG_VD                              0x1E2D
#define REG_CKG_VDS                             0x1E2E
#define REG_CKG_HDC                             0x1E2F
#define REG_CKG_FICLK                           0x1E30
#define REG_CKG_PCM                             0x1E31
#define REG_CKG_PCI                             0x1E32
#define REG_CKG_VE                              0x1E33
#define REG_CKG_SDRDAC                          0x1E34
#define REG_CKG_FCLK                            0x1E35
#define REG_CKG_FMCLK                           0x1E36
#define REG_CKG_ODCLK                           0x1E37
#define REG_CKG_VEIN                            0x1E38
#define REG_CKG_FCIE                            0x1E39
#define REG_CKG_TS                              0x1E3A
#define REG_CKG_IDCLK1                          0x1E3E
#define REG_CKG_IDCLK2                          0x1E3F
#define REG_CKG_STRLD                           0x1E44
#define REG_CKG_MCU                             0x1E45
#define REG_SW_VDMCU                            0x1E4C
#define REG_CKG_DHC0                            0x1E58
#define REG_CKG_DHC1                            0x1E59

#define REG_DC0_NUM0                            0x1E40
#define REG_DC0_NUM1                            0x1E41
#define REG_DC0_DEN0                            0x1E42
#define REG_DC0_DEN1                            0x1E43

#define REG_GPIO_IN_LOW                         0x1E60
#define REG_GPIO_IN_HIGH                        0x1E61
#define REG_GPIO_OUT_LOW                        0x1E62
#define REG_GPIO_OUT_HIGH                       0x1E63
#define REG_GPIO_OE_0                           0x1E64
#define REG_GPIO_OE_1                           0x1E65

#define REG_FCIE_IS_GPIO_IN_0                   0x1E66
#define REG_FCIE_IS_GPIO_IN_1                   0x1E67
#define REG_FCIE_IS_GPIO_OUT_0                  0x1E68
#define REG_FCIE_IS_GPIO_OUT_1                  0x1E69
#define REG_FCIE_IS_GPIO_OE_0                   0x1E6A
#define REG_FCIE_IS_GPIO_OE_1                   0x1E6B

#define REG_TS1_GPIO_IN                         0x1E72
#define REG_TS1_GPIO_OUT                        0x1E74
#define REG_TS1_GPIO_OE                         0x1E76

#define REG_DI_GPIO_IN_LOW                      0x1E78
#define REG_DI_GPIO_IN_HIGH                     0x1E79
#define REG_DI_GPIO_OUT_0                       0x1E7A
#define REG_DI_GPIO_OUT_1                       0x1E7B
#define REG_DI_GPIO_OE_LOW                      0x1E7C
#define REG_DI_GPIO_OE_HIGH                     0x1E7D

// 070419 SK GPIO PORT
#define REG_I2S_GPIO_IN_LOW                     0x1E7E
#define REG_I2S_GPIO_IN_HIGH                    0x1E7F
#define REG_I2S_GPIO_OUT_LOW                    0x1E80
#define REG_I2S_GPIO_OUT_HIGH                   0x1E81
#define REG_I2S_GPIO_OE_LOW                     0x1E82
#define REG_I2S_GPIO_OE_HIGH                    0x1E83

#define REG_PCI_GPIO_IN_0                       0x1E84
#define REG_PCI_GPIO_IN_1                       0x1E85
#define REG_PCI_GPIO_IN_2                       0x1E86

#define REG_PCI_GPIO_OUT_0                      0x1E8A  //pci 0..7
#define REG_PCI_GPIO_OUT_1                      0x1E8B  //pci 8..f
#define REG_PCI_GPIO_OUT_2                      0x1E8C  //pci 16..23

#define REG_PCI_GPIO_OE_0                       0x1E90
#define REG_PCI_GPIO_OE_1                       0x1E91
#define REG_PCI_GPIO_OE_2                       0x1E92

#define REG_MUX_FUNC_SEL0                       0x1EA0
#define REG_MUX_FUNC_SEL1                       0x1EA1
#define REG_MUX_FUNC_SEL2                       0x1EA2
#define REG_MUX_FUNC_SEL3                       0x1EA3
#define REG_P1_ENABLE                           0x1EA4
#define REG_TEMP_SENSE                          0x1EA4

#define REG_MUX_FUNC_SEL6                       0x1EA6
#define REG_MUX_FUNC_SEL7                       0x1EA7

#define REG_MUX_UART_JTAG                       0x1EAA

#define REG_MUX_VD_GPIO_SEL0                    0x1EAC
#define REG_MUX_VD_GPIO_SEL1                    0x1EAD
#define REG_MUX_VD_GPIO_SEL2                    0x1EAE
#define REG_MUX_VD_GPIO_SEL3                    0x1EAF

#define REG_MUX_TOP0_GPIO                       0x1EB0
#define REG_TOP0_GPIO_R                         0x1EB1
#define REG_MUX_TOP1_GPIO                       0x1EB2
#define REG_TOP1_GPIO_R                         0x1EB3
#define REG_MUX_TOP2_GPIO                       0x1EB4
#define REG_TOP2_GPIO_R                         0x1EB5
#define REG_MUX_TOP3_GPIO                       0x1EB6
#define REG_TOP3_GPIO_R                         0x1EB7
#define REG_MUX_TOP4_GPIO                       0x1EB8
#define REG_TOP4_GPIO_R                         0x1EB9
#define REG_MUX_TOP5_GPIO                       0x1EBA
#define REG_TOP5_GPIO_R                         0x1EBB

#define REG_MUX_DTCON_GPIO_SEL                  0x1EBC
#define REG_MUX_UART_PWM_SEL                    0x1EBD
#define REG_CENTRAL_EN                          0x1EBE

#define REG_MUX_TOP6_GPIO                       0x1EC8
#define REG_TOP6_GPIO_R                         0x1EC9

#define REG_DEVICE_ID_MAJOR                     0x1ECC
#define REG_DEVICE_ID_MINOR                     0x1ECD
#define REG_CHIP_VERSION                        0x1ECE
#define REG_CHIP_REVISION                       0x1ECF

#define REG_MUX_PCI                             0x1EE0

//--------------------------------------------------
//REG_CENTRAL_EN    // kevin 20070822
#define VD_SWRGBOUT_EN                          BIT7
#define SECOND_OP_SYNCO_COEN					BIT6
#define SECOND_BOUT_COEN						BIT5
#define BOUT_COEN                               BIT4
#define GPO_COEN                                BIT3
#define OP_SYNCO_COEN                           BIT2
#define GPIO_COEN                               BIT1
#define VD_SYNCO_COEN                           BIT0

//--------------------------------------------------
//REG_MUX_CONFIG_0
#define DI_MODE_IS_BT656                        (BIT3|BIT2)
#define TS0_IS_DI                               BIT5
#define TS0_IS_TS0                              BIT6
#define UTMI_MODE                               BIT7

//-----------------------
//REG_MUX_CONFIG_1
#define UTMI_PHY_MODE                           BIT1

//-----------------------------------------------
//definition for REG_MUX_CONFIG_3
#define SECOND_UART_MODE                         (BIT0|BIT1)
#define SECOND_UART_MODE_1                       BIT1
#define PCM2CONFIG                               (BIT2|BIT3)

#define I2S_MUTE_MODE                           (BIT7|BIT6)
#define I2S_MUTE_MODE_0                         BIT6
#define I2S_MUTE_MODE_1                         BIT7
#define I2S_OUT_MUTE_USE_PAD_LHSYNC2            BIT6
#define I2S_OUT_MUTE_USE_PAD_PCI_AD8            BIT7 | BIT7



#define        PAD_PCMCIA                       0xFC  //bit0~1 clear

//-----------------------------------------------
//definition for REG_MUX_CONFIG_4
#define FCIE_CONFIG                             (BIT7|BIT6)
#define FCIE_MODE_1                             (BIT6)
#define FCIE_MODE_2                             (BIT7)

//-----------------------------------------------
//definition for REG_MUX_CONFIG_5
#define DSPE_JTAG_MODE                          (BIT3|BIT2)
#define PWM0_ENABLE                             BIT4
#define PWM1_ENABLE                             BIT5
#define PWM2_ENABLE                             BIT6
#define PWM3_ENABLE                             BIT7






//--------------------------------------------------
// REG_MUX_FUNC_SEL0
#define PWM2_SETTING                            BIT0
#define PWM3_SETTING                            BIT1
#define ATCON_SETTING                           (BIT2|BIT3)
#define DTCON_SETTING                           (BIT4|BIT5)
#define TCON_IS_GPIO                            (BIT6)

//--------------------------------------------------
//REG_MUX_FUNC_SEL1
#define PAD_IIC2                                BIT1
#define CEC_MODE                                (BIT3|BIT4)


//--------------------------------------------------
//definition for REG_MUX_FUNC_SEL2  //reg[1ea2]
#define PWM0_IS_GPIO                            0x01
#define PWM1_IS_GPIO                            0x02
#define PWM2_IS_GPIO                            0x04
#define PWM3_IS_GPIO                            0x08
#define CI_PCM_A4TOA14_IS_GPIO_0                0x10
#define CI_PCM_A4TOA14_IS_GPIO_1                0x20
#define IR_IN_IS_GPIO                           0x40
#define INT_IS_GPIO                             0x80

//-------------------------------------------
//definition for REG_MUX_FUNC_SEL3   //reg[1ea3]
#define IR_IN2_IS_GPIO                          BIT0
#define INT2_IS_GPIO                            BIT1
#define TS0_IS_GPIO                             BIT2
#define TS1_IS_GPIO                             BIT3
#define DI_IS_GPIO                              BIT4
#define I2S_IS_GPIO                             BIT5
#define FLHWE_IS_GPIO                           BIT6
#define FCIE_IS_GPIO                            BIT7

//--------------------------------------------------
//REG_MUX_FUNC_SEL6
#define DHC_DFT_MODE                            BIT1

//--------------------------------------------------
// REG_MUX_UART_JTAG
#define JTAG_FOR_51                            0x00
#define JTAG_FOR_AEON                          BIT0
#define JTAG_FOR_TSP                           BIT1

#define UART0_SEL_51_UART0                     0x00
#define UART0_SEL_51_UART1                     BIT2
#define UART0_SEL_VD_UART0                     BIT3
#define UART0_SEL_AEON                         (BIT2|BIT3)
#define UART0_SEL_TSP                          BIT4

#define UART1_SEL_51_UART0                     0x00
#define UART1_SEL_51_UART1                     BIT5
#define UART1_SEL_VD_UART0                     BIT6
#define UART1_SEL_AEON                         (BIT5|BIT6)
#define UART1_SEL_TSP                          (BIT7)

//--------------------------------------------------
//definition for REG_MUX_PCI   //reg[1ee0]
#define PCI_GPIO_0                              BIT0
#define PCI_GPIO_1                              BIT1
#define PCI_GPIO_2                              BIT2

// MISC
//------------------------------------------------------------------------------
// definition for REG_CT_MISC0      //reg[0x1e22]
#define MISC_MCU_CLKSEL_MASK                    0x01    // MASK
#define MISC_MCU_CLKSEL_DFT                     0x00
#define MISC_MCU_CLKSEL_EX                      0x01
#define MISC_VD_CLKSEL_MASK                     0x02    // MASK
#define MISC_VD_CLKSEL_VDADC                    0x00
#define MISC_VD_CLKSEL_ADC                      0x02
#define MISC_DE_ONLY_F1                         0x04
#define MISC_DE_ONLY_F2_SCTOP                   0x08
#define MISC_USBSYN_RST                         0x10
#define MISC_STC0SYN_RST                        0x20
#define MISC_STC0CWSEL_MASK                     0x80    // MASK
#define MISC_STC0CWSEL_HKMCU                    0x00
#define MISC_STC0CWSEL_TSP                      0x80
//--------------------------------------------------

// definition for REG_CT_MISC1      //reg[0x1e23]
#define MISC_UPDATE_STC0CW                      0x02
#define MISC_UPDATE_DC0CW_FRUN                  0x08
#define MISC_UPDATE_DC0CW_SYNC                  0x40