📄 hwreg_s2.h
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////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2006-2007 MStar Semiconductor, Inc.
// All rights reserved.
//
// Unless otherwise stipulated in writing, any and all information contained
// herein regardless in any format shall remain the sole proprietary of
// MStar Semiconductor Inc. and be kept in strict confidence
// (¨MStar Confidential Information〃) by the recipient.
// Any unauthorized act including without limitation unauthorized disclosure,
// copying, use, reproduction, sale, distribution, modification, disassembling,
// reverse engineering and compiling of the contents of MStar Confidential
// Information is unlawful and strictly prohibited. MStar hereby reserves the
// rights to any and all damages, losses, costs and expenses resulting therefrom.
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _HWREG_S2_H
#define _HWREG_S2_H
//------------------------------------------------------------------------------
// Base Address
//------------------------------------------------------------------------------
#define ISP_REG_BASE 0x0800
#define AEON_REG_BASE 0x0F00
#define MCU_REG_BASE 0x1000 // seven 070822_00
#define MVD_REG_BASE 0x1100
#define MIU_REG_BASE 0x1200
#define VD_MCU_REG_BASE 0x1300
#define MVOP_REG_BASE 0x1400
#define TSP0_REG_BASE 0x1500
#define IP1_16_REG_BASE 0x1600
#define TOUCHPL_REG_BASE 0x1900
#define OP2_DITH_REG_BASE 0x1C00
#define OP2_PIP_REG_BASE 0x1D00
#define CHIP_REG_BASE 0x1E00
#define GOP_REG_BASE 0x1F00
#define FCIE0_REG_BASE 0x2000
#define FCIE1_REG_BASE 0x2100
#define FCIE2_REG_BASE 0x2200
#define FCIE3_REG_BASE 0x2300
#define USB0_REG_BASE 0x2400
#define ADC_ATOP_REG_BASE 0x2500
#define ADC_DTOP_REG_BASE 0x2600
#define HDMI_REG_BASE 0x2700
#define GE_REG_BASE 0x2800
#define CI_REG_BASE 0x2A00
#define IRQ_REG_BASE 0x2B00
#define CACHE_REG_BASE 0x2B80
#define XDMIU_REG_BASE 0x2BC0
#define VIVALDI0_REG_BASE 0x2C00
#define VIVALDI1_REG_BASE 0x2D00
#define SC0_REG_BASE 0x2E00
#define SC1_REG_BASE 0x2F00
#define SC2_REG_BASE 0x3000
#define SC3_REG_BASE 0x3100
#define SC4_REG_BASE 0x3200
#define M4VD_REG_BASE 0x3300
#define MAILBOX_REG_BASE 0x3380
#define DLL_REG_BASE 0x3400
#define IIC_REG_BASE 0x3420
#define PCM_REG_BASE 0x3440
#define PM_REG_BASE 0x3400// kevin 20070912
#define MIIC_PM_PWM_ECC_BASE 0x3400// kevin 20070913
#define PWM_REG_BASE 0x3460
#define RTC_REG_BASE 0x3480
#define ECC_REG_BASE 0x34E0
#define AFEC_REG_BASE 0x3500
#define COMB_REG_BASE 0x3600
#define VBI_REG_BASE 0x3700
#define SCM_REG_BASE 0x3800
#define CCFL_REG_BASE 0x3900
#define PATGEN_REG_BASE 0x3980
#define SAR_REG_BASE 0x3A00
#define VE0_REG_BASE 0x3B00
#define PIU_MISC_REG_BASE 0x3C00
#define DDC_REG_BASE 0x3D00
#define IR_REG_BASE 0x3D80
#define VE1_REG_BASE 0x3E00
#define VE2_REG_BASE 0x3F00
//------------------------------------------------------------------------------
// MCU and PIU Reg
//------------------------------------------------------------------------------
#define AEON_REG_CTRL 0x0FF0
//---------------------------------------------
// definition for AEON_REG_CTRL //reg[0x0FF0]
#define AEON_CTRL_EN BIT0
#define AEON_CTRL_RST BIT1
#define AEON_DWB_SWAP BIT3
#define AEON_SPI_ADDR0 0x0FFE
#define AEON_SPI_ADDR1 0x0FFF
//------------------------------------------------------------------------------
//PLL control in ATOP
//------------------------------------------------------------------------------
#define PLL_CONTROL_IN_ATOP 0x2510
//------------------------------------------------------------------------------
// MCU and PIU Reg (0x1000)
//------------------------------------------------------------------------------
#define DRAM_START_ADDR_0 0x100C
#define DRAM_START_ADDR_1 0x100D
#define DRAM_START_ADDR_2 0x1008
#define DRAM_START_ADDR_3 0x1009
#define DRAM_END_ADDR_0 0x100E
#define DRAM_END_ADDR_1 0x100F
#define DRAM_END_ADDR_2 0x100A
#define DRAM_END_ADDR_3 0x100B
#define SPI_START_ADDR_0 0x1014
#define SPI_START_ADDR_1 0x1015
#define SPI_START_ADDR_2 0x1010
#define SPI_START_ADDR_3 0x1011
#define SPI_END_ADDR_0 0x1016
#define SPI_END_ADDR_1 0x1017
#define SPI_END_ADDR_2 0x1012
#define SPI_END_ADDR_3 0x1013
#define ROM_CODE_CTRL 0x1018
#define SRAM_ENABLE 0x01
#define SPI_ENABLE 0x02
#define DRAM_ENABLE 0x04
#define ICACHE_REST 0x08
#define MCU_BANK_USE_XFR 0x80
#define ROM_BANK_ADR 0x1019
#define REG_RESET_CPU_8051 0x1080
#define REG_RESET_CPU_AEON 0x1082
#define REG_SW_RESET_CPU_8051 0x1084
#define REG_SW_RESET_CPU_AEON 0x1086
//---------------------------------------------
// definition for REG_SW_RESET_CPU_AEON //reg[0x1086]
#define AEON_SW_RESET BIT0
//------------------------------------------------------------------------------
// MVD Reg
//------------------------------------------------------------------------------
#define MVD_CTRL 0x1100
#define MVD_STATUS 0x1101
#define MVD_COMMAND 0x1102
#define MVD_ARG0 0x1104
#define MVD_ARG1 0x1105
#define MVD_ARG2 0x1106
#define MVD_ARG3 0x1107
//------------------------------------------------------------------------------
// MVOP Reg
//------------------------------------------------------------------------------
#define VOP_FRAME_VCOUNT 0x1400
#define VOP_FRAME_HCOUNT 0x1402
#define VOP_VB0_STR 0x1404
#define VOP_VB0_END 0x1406
#define VOP_VB1_STR 0x1408
#define VOP_VB1_END 0x140A
#define VOP_TF_STR 0x140C
#define VOP_BF_STR 0x140E
#define VOP_HACT_STR 0x1410
#define VOP_IMG_HSTR 0x1412
#define VOP_IMG_VSTR0 0x1414
#define VOP_IMG_VSTR1 0x1416
#define VOP_TF_VS 0x1418
#define VOP_BF_VS 0x141A
#define VOP_HI_TSH 0x1420
#define VOP_CTRL0 0x1422
#define VOP_TST_IMG 0x1424
#define VOP_U_PAT 0x1426
#define VOP_INT_MASK 0x143E
#define VOP_MPG_JPG_SWITCH 0x1440
#define VOP_JPG_YSTR0_L 0x1442
#define VOP_JPG_YSTR0_H 0x1444
#define VOP_JPG_UVSTR0_L 0x1446
#define VOP_JPG_UVSTR0_H 0x1448
#define VOP_JPG_HSIZE 0x144A
#define VOP_JPG_VSIZE 0x144C
#define VOP_REG_WR 0x144E
#define VOP_DEBUG_R 0x145E
#define VOP_JPG_YSTR1_L 0x1462
#define VOP_JPG_YSTR1_H 0x1464
#define VOP_JPG_UVSTR1_L 0x1466
#define VOP_JPG_UVSTR1_H 0x1468
//------------------------------------------------------------------------------
// VD MCU control register in Saturn2
//------------------------------------------------------------------------------
#define VD_MCU_OFFSET_ADDR_0 0x1300
#define VD_MCU_OFFSET_ADDR_1 0x1301
#define VD_MCU_PAGE_ADDR 0x1302
#define VD_MCU_WDATA 0x1304
#define VD_MCU_WDATA_CTRL 0x1305
#define VD_MCU_RDATA 0x1306
#define VD_MCU_RDATA_CTRL 0x1307
#define VD_MCU_ADDR_CTRL 0x1308
#define VD_MCU_READ_WRITE 0x130A
#define VD_MCU_RESET 0x130C
//------------------------------------------------------------------------------
// IRQ controller
//------------------------------------------------------------------------------
#define EX0_INT_MASK 0x2B00
#define EX0_INT_CLEAR_0 0x2B08
#define EX0_INT_CLEAR_1 0x2B09
#define EX0_INT_CLEAR_2 0x2B0A
#define EX0_INT_CLEAR_3 0x2B0B
#define EX0_INT_FINAL_STATUS_0 0x2B10
#define EX0_INT_FINAL_STATUS_1 0x2B11
#define EX0_INT_FINAL_STATUS_2 0x2B12
#define EX0_INT_FINAL_STATUS_3 0x2B13
#define EX1_INT_MASK 0x2B18
#define EX1_INT_FINAL_STATUS_0 0x2B28
#define EX1_INT_FINAL_STATUS_1 0x2B29
#define EX1_INT_FINAL_STATUS_2 0x2B2A
#define EX1_INT_FINAL_STATUS_3 0x2B2B
#define REG_C_FIQ_FORCE_0 0x2B04
#define REG_C_FIQ_FORCE_1 0x2B05
#define REG_AEON_C_FIQ_FORCE_0 0x2B44
#define REG_AEON_C_FIQ_FORCE_1 0x2B45
//------------------------------------------------------------------------------
// ISP
//------------------------------------------------------------------------------
#define ISP_BASE 0x800
#define REG_SFSH_ISP_PASSWORD 0x0800 //ISP / XIU read / DMA mutual exclusive
#define REG_SFSH_SPI_COMMAND 0x0802
#define REG_SFSH_ADDRESS21 0x0804 //A[15:0]
#define REG_SFSH_ADDRESS3 0x0806 //A[23:16]
#define REG_SFSH_WDATA 0x0808
#define REG_SFSH_RDATA 0x080A
#define REG_SFSH_SPI_CLK_DIV 0x080C
#define REG_SFSH_DEV_SEL 0x080E
#define REG_SFSH_SPI_CE_CLR 0x0810
#define REG_SFSH_SPI_RD_REQ 0x0818
#define REG_SFSH_ENDIAN_SEL_SPI 0x081E
#define REG_SFSH_SPI_RD_DATA_RDY 0x082A
#define REG_SFSH_SPI_WR_DATA_RDY 0x082C
#define REG_SFSH_SPI_WR_CMD_RDY 0x082E
#define REG_SFSH_TRIGGER_MODE 0x0854
//------------------------------------------------------------------------------
// chip top
//------------------------------------------------------------------------------
#define REG_MUX_CONFIG_0 0x1E02
#define REG_MUX_CONFIG_1 0x1E03
#define REG_MUX_CONFIG_2 0x1E04
#define PCI_CONFIG (BIT0|BIT1)
#define INT_USE_PAD_INT 0x00
#define INT_USE_PAD_INT2 BIT2
#define IR_USE_PAD_IRIN 0x00
#define IR_USE_PAD_IRIN2 BIT3
#define TEST_IN_MODE (BIT5|BIT4)
#define TEST_OUT_MODE (BIT7|BIT6)
#define REG_MUX_CONFIG_3 0x1E05
#define REG_MUX_CONFIG_4 0x1E06
#define REG_MUX_CONFIG_5 0x1E07
#define REG_CT_MISC0 0x1E22
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