drvsf.h

mstar 776 开发的车载dvd

////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2006-2007 MStar Semiconductor, Inc.
// All rights reserved.
//
// Unless otherwise stipulated in writing, any and all information contained
// herein regardless in any format shall remain the sole proprietary of
// MStar Semiconductor Inc. and be kept in strict confidence
// (¨MStar Confidential Information〃) by the recipient.
// Any unauthorized act including without limitation unauthorized disclosure,
// copying, use, reproduction, sale, distribution, modification, disassembling,
// reverse engineering and compiling of the contents of MStar Confidential
// Information is unlawful and strictly prohibited. MStar hereby reserves the
// rights to any and all damages, losses, costs and expenses resulting therefrom.
//
// Description: Section Filter Driver
//
////////////////////////////////////////////////////////////////////////////////

#ifndef _DRV_SF_H_
#define _DRV_SF_H_

#include "datatype.h"
#include "debug.h"

#if (PLATFORM != MCU8051) //================================================<<<
#include "hw_sf.h"
#else //<<<=================================================================>>>
#include "sysinfo.h"

#define HW_SF_MAX_FLT_NUMBER			32
#define HW_SF_GENERAL_FLT_NUMBER		8                                                                               //1K  -Filter
#define HW_SF_RESERVE_FLT_NUMBER        16                                                                              //Aeon-Filter
#define HW_SF_SPECIAL_FLT_NUMBER		(HW_SF_MAX_FLT_NUMBER - HW_SF_GENERAL_FLT_NUMBER - HW_SF_RESERVE_FLT_NUMBER)    //4K  -Filter

#define HW_SF_SECTION_1K    (1024+512)  //<---for getting 1K-section that size > (1024-8)
#define HW_SF_SECTION_4K	16384

#define HW_SF_MATCH_PATTERN_LENGTH		16

#define HW_SF_REG_LENGTH				32			//32-bit x 32
#define HW_SF_REG_CTRL_OFFSET		 	0			//8-bit
#define	HW_SF_REG_MATCH0_OFFSET		 	4			//8-bit
#define HW_SF_REG_MATCH1_OFFSET		 	8			//8-bit
#define HW_SF_REG_MATCH2_OFFSET		 	12			//8-bit
#define HW_SF_REG_MATCH3_OFFSET			16			//8-bit
#define	HW_SF_REG_MASK0_OFFSET		 	20			//8-bit
#define HW_SF_REG_MASK1_OFFSET		 	24			//8-bit
#define HW_SF_REG_MASK2_OFFSET		 	28			//8-bit
#define HW_SF_REG_MASK3_OFFSET		 	32			//8-bit
#define HW_SF_REG_START_OFFSET		 	36			//8-bit
#define HW_SF_REG_END_OFFSET		 	40			//8-bit
#define HW_SF_REG_READ_OFFSET		 	44			//8-bit
#define HW_SF_REG_WRITE_OFFSET			48			//8-bit
#define HW_SF_REG_CURRENT_OFFSET		52			//8-bit
#define HW_SF_REG_REQUEST_OFFSET		56			//8-bit
#define HW_SF_REG_CRC_OFFSET			60			//8-bit
#define	HW_SF_REG_NMATCH0_OFFSET		64			//8-bit
#define HW_SF_REG_NMATCH1_OFFSET		68			//8-bit
#define HW_SF_REG_NMATCH2_OFFSET	 	72			//8-bit
#define HW_SF_REG_NMATCH3_OFFSET		76			//8-bit

#define HW_SF_REG_CTRL_BIT_FILTER_LAYER	    0x00000007
#define HW_SF_REG_CTRL_BIT_FILTER_SECTION   0x00000000
#define HW_SF_REG_CTRL_BIT_FILTER_PES	    0x00000001
#define HW_SF_REG_CTRL_BIT_FILTER_TS	    0x00000002
#define HW_SF_REG_CTRL_BIT_FILTER_AF	    0x00000003
#define HW_SF_REG_CTRL_BIT_FILTER_TTX	    0x00000004
#define HW_SF_REG_CTRL_BIT_FILTER_OAD	    0x00000005
#define HW_SF_REG_CTRL_BIT_FILTER_TSPUSI    0x00000006
#define HW_SF_REG_CTRL_BIT_EXCLUDE_MATCH    0x00000008

#define HW_SF_REG_REQUEST_BIT_REQUEST	    0x0000ffff
#define HW_SF_REG_REQUEST_BIT_REMAIN	    0xffff0000

//========================= 8051/AEON INTERFACE =============================//
#define TSP_SEMAPHORE_PROTECT   1
#if (TSP_SEMAPHORE_PROTECT == 1)

#define INIT_TSP_ACCESS                 \
XBYTE[0x1591] = 0;                      \
XBYTE[0x15A4] = 0;                      \
XBYTE[0x15A6] = 0;

#define WAIT_TSP_ACCESS                 \
XBYTE[0x1591] = 0xff;                   \
XBYTE[0x15A4] = 0xff;                   \
while(XBYTE[0x15A6] && XBYTE[0x15A4]);  \
XBYTE[0x1591] = 0xff;//prevent 51 flag is changed by aeon

#define TTX_WAIT_TSP_ACCESS             \
XBYTE[0x1591]

#define RELEASE_TSP_ACCESS              \
XBYTE[0x1591] = 0x00;

#else

#define INIT_TSP_ACCESS                 \
do{                                     \
}while(0)

#define WAIT_TSP_ACCESS                 \
do{                                     \
}while(0)

#define RELEASE_TSP_ACCESS              \
do{                                     \
}while(0)

#endif
//========================= 8051/AEON INTERFACE =============================//

#endif//PLATFORM_MCU8051 //=================================================>>>

/*definition ====================================================================================*/
#define DRV_SF_MAX_FLT_NUMBER			HW_SF_MAX_FLT_NUMBER

/*enumeration ===================================================================================*/
enum DRV_SF_LAYER
{
	DRV_SF_LAYER_SEC		= 0x00,
	DRV_SF_LAYER_PES		= 0x01,
	DRV_SF_LAYER_TS			= 0x02,
	DRV_SF_LAYER_PCR		= 0x03,
	DRV_SF_LAYER_TTX		= 0x04,
	DRV_SF_LAYER_OAD		= 0x05,
	DRV_SF_LAYER_TSPUSI     = 0x06
};

enum DRV_SF_TYPE
{
	DRV_SF_TYPE_VIDEO		     =  1,
	DRV_SF_TYPE_AUDIO		     =  2,
	DRV_SF_TYPE_SUBTITLE	     =  3,
	DRV_SF_TYPE_TELETEXT	     =  4,
	DRV_SF_TYPE_PES			     =  5,
	DRV_SF_TYPE_SECTION_1K	     =  6,
	DRV_SF_TYPE_SECTION_4K	     =  7,
	DRV_SF_TYPE_PCR			     =  8,
	DRV_SF_TYPE_PACKET		     =  9,
	DRV_SF_TYPE_PACKET_PUSI      = 10,
	DRV_SF_TYPE_OAD			     = 11,
	DRV_SF_TYPE_RECORD		     = 12,
	DRV_SF_TYPE_PLAYBACK         = 13
};

/*function ======================================================================================*/
#ifdef DRV_SF
#define DRV_SF_INTERFACE
#else
#define	DRV_SF_INTERFACE extern
#endif

DRV_SF_INTERFACE void MDrv_Sf_SetFilterLayer(U8 SecFltNo, U8 Layer);
DRV_SF_INTERFACE void MDrv_Sf_SetPattern(U8 SecFltNo, U8 *pMatch, U8 *pMask, U8 *pNotMatch);
DRV_SF_INTERFACE void MDrv_Sf_SetBuffer(U8 SecFltNo, U32 StartAddress, U32 BufferSize);
DRV_SF_INTERFACE U32  MDrv_Sf_GetStartAddress(U8 SecFltNo);
DRV_SF_INTERFACE U32  MDrv_Sf_GetEndAddress(U8 SecFltNo);
DRV_SF_INTERFACE U32  MDrv_Sf_GetBufferSize(U8 SecFltNo);
DRV_SF_INTERFACE void MDrv_Sf_SetReadAddress(U8 SecFltNo, U32 ReadAddress);
DRV_SF_INTERFACE U32  MDrv_Sf_GetReadAddress(U8 SecFltNo);
DRV_SF_INTERFACE void MDrv_Sf_SetWriteAddress(U8 SecFltNo, U32 WriteAddress);
DRV_SF_INTERFACE U32  MDrv_Sf_GetWriteAddress(U8 SecFltNo);

#ifdef TELETEXT
DRV_SF_INTERFACE U32  MDrv_Sf_GetTeletextWriteAddress(U8 SecFltNo);
#endif

DRV_SF_INTERFACE void MDrv_Sf_ResetBuffer(U8 SecFltNo);
DRV_SF_INTERFACE void MDrv_Sf_SetRequest(U8 SecFltNo, U16 ReqCount);
DRV_SF_INTERFACE U16  MDrv_Sf_GetRequest(U8 SecFltNo);

#if (PLATFORM != MCU8051) //================================================<<<
DRV_SF_INTERFACE void MDrv_Sf_UpdateHwCrc32Result(U8 SecFltNo);
#endif//PLATFORM_MCU8051 //=================================================>>>

#if (PLATFORM != MCU8051) //================================================<<<
DRV_SF_INTERFACE U32  MDrv_Sf_GetHwCrc32Result(U8 SecFltNo);
#else //<<<=================================================================>>>
DRV_SF_INTERFACE U8  MDrv_Sf_GetHwCrc32Result(U8 SecFltNo);
#endif//PLATFORM_MCU8051 //=================================================>>>

DRV_SF_INTERFACE void MDrv_Sf_InitialFilter(U8 SecFltNo, U8 FilterType);
DRV_SF_INTERFACE void MDrv_Sf_Initial(void);
DRV_SF_INTERFACE void MDrv_Sf_RegisterTest(void);

/*===============================================================================================*/

#endif // _DRV_SF_H_