ms_reg.h

mstar 776 开发的车载dvd

#define INTCTRL		0xCA
#define INTPULSE	0xCB
// intput status
#define INSTA		0xCC
#define INSTB		0xCD
#define INTENA		0xCE
#define INTENB		0xCF
// Clock generator
#define PLLCTRL1	0xD0
	#define BPM_B	BIT3
	#define EOCK_B	BIT6
	#define XOUT_B	BIT7
#define PLLCTRL2	0xD1
	#define MP_PD_B		BIT0 // Master PLL Power down
	#define MP_RST_B	BIT1 // Master PLL reset
	#define MP_POR_B	BIT2 // Master PLL power on reset
	#define MP_K_B		BIT3 // Master PLL Post divider
	#define LP_PD_B		BIT4 // output PLL power down
	#define LP_RST_B	BIT5 // output PLL reset
	#define LP_POR_B	BIT6 // output PLL power on reset

#define	MPLL_M		0xD2
#define	LPLL_M		0xD3
#define	LPLL_CTL2	0xD4
#define	LPLL_SET_L	0xD5
#define	LPLL_SET_M	0xD6
#define	LPLL_SET_H	0xD7
#define	LPLL_STEP_L	0xD8
#define	LPLL_STEP_H	0xD9
#define	LPLL_SPAN_L	0xDA
#define	LPLL_SPAN_H	0xDB

// mode detect status
#define STATUS1		0xE0
#define STATUS2		0xE1
		#define INTM_B	BIT3
		#define SOGD_B	BIT4
		#define CSD_B	BIT5
		#define SOGP_B	BIT6
		#define CSP_B	BIT7
#define VTOTAL_L	0xE2
#define VTOTAL_H	0xE3
#define HSPRD_L		0xE4
#define HSPRD_H		0xE5
// Sync Change tolerance
#define HSTOL		0xE6
#define VSTOL		0xE7
// status override/interlace detect
#define ISOVRD		0xE8
#define MDCTRL		0xE9

//------------------- Misc control (13, EEh-F6h)
// Coast control
#define COCTRL1		0xED
#define COCTRL2		0xEE
#define COCTRL3		0xEF
// Power down control/ software reset
#define PDMD		0xF0
	#define	PDDS_B	BIT4

#define SWRST		0xF1
	#define SWR_B	BIT0
	#define OSDR_B	BIT1
	#define BIUR_B	BIT2
	#define DPR_B	BIT3
	#define GPR_B	BIT4
	#define ADCR_B	BIT5
// output signal control
#define OSCTRL		0xF2
// intput signal contorl
#define ISCTRL		0xF3
	#define	SCKI_B	BIT0	// input sample clock invert
	#define	CSDM_B	BIT1	// composite syn detect mode
	#define	ISSM_B	BIT2	// input sync sample mode
	#define	HSFL_B	BIT3	// input hsync filter
	#define	DEGE_B	BIT7	// enable DE Glitch
// output tri-state control
#define TRISTATE	0xF4
// output driving current control
#define ODRV		0xF5
// Even clock delay control
#define ECLKDLY		0xF6
// chip ID
#define CHIPID		0xFE

//---------------------------OSD register-------------------
// osd double buffer control
#define OSDDBC		0x01
// osd start position
#define OHSTA_L		0x02
#define OHSTA_H		0x03
#define OVSTA_L		0x04
#define OVSTA_H		0x05
// osd size controol
#define OSDW		0x06
#define OSDH		0x07
// osd space control
#define OHSPA		0x08
#define OVSPA		0x09
#define OSPW		0x0A
#define OSPH		0x0B
// internal osd control
#define IOSDC1		0x0C
	#define	MWIN_B	BIT0
#define IOSDC2		0x0D
#define IOSDC3		0x0E
//osd windodw shadow control
#define OSDHC		0x0F
//osd code buffer offset/ base address
#define OCBUFO		0x12
#define OSDBA_L		0x13
#define OSDBA_H		0x14
// osd gradually color control
#define GCCTRL		0x15
#define GRADCLR		0x16
// osd horizontal gradullay color
#define HGRADCR		0x17
#define HGRADCG		0x18
#define HGRADCB		0x19
#define HGRADSR		0x1A
#define HGRADSG		0x1B
#define HGRADSB		0x1C
// osd vertical gradullay color
#define VGRADCR		0x1D
#define VGRADCG		0x1E
#define VGRADCB		0x1F
#define VGRADSR		0x20
#define VGRADSG		0x21
#define VGRADSB		0x22
// osd sub window 0 control
#define SUBW0C		0x23
#define SW0HST		0x24
#define SW0HEND		0x25
#define SW0VST		0x26
#define SW0VEND		0x27
#define SUBW0A		0x28
// osd sub window 1 control
#define SUBW1C		0x29
#define SW1HST		0x2A
#define SW1HEND		0x2B
#define SW1VST		0x2C
#define SW1VEND		0x2D
#define SUBW1A		0x2E
// osd sub window 2 control
#define SUBW2C		0x2F
#define SW2HST		0x30
#define SW2HEND		0x31
#define SW2VST		0x32
#define SW2VEND		0x33
#define SUBW2A		0x34
// osd sub window 3 control
#define SUBW3C		0x35
#define SW3HST		0x36
#define SW3HEND		0x37
#define SW3VST		0x38
#define SW3VEND		0x39
#define SUBW3A		0x3A
// osd row attribute
#define	ROW00A		0x3B
#define	ROW01A		0x3C
#define	ROW02A		0x3D
#define	ROW03A		0x3E
#define	ROW04A		0x3F
#define	ROW05A		0x40
#define	ROW06A		0x41
#define	ROW07A		0x42
#define	ROW08A		0x43
#define	ROW09A		0x44
#define	ROW0AA		0x45
#define	ROW0BA		0x46
#define	ROW0CA		0x47
#define	ROW0DA		0x48
#define	ROW0EA		0x49

// osd color palette
#define CLR0R		0x58
#define CLR0G		0x59
#define CLR0B		0x5A
#define CLR1R		0x5B
#define CLR1G		0x5C
#define CLR1B		0x5D
#define CLR2R		0x5E
#define CLR2G		0x5F
#define CLR2B		0x60
#define CLR3R		0x61
#define CLR3G		0x62
#define CLR3B		0x63
#define CLR4R		0x64
#define CLR4G		0x65
#define CLR4B		0x66
#define CLR5R		0x67
#define CLR5G		0x68
#define CLR5B		0x69
#define CLR6R		0x6A
#define CLR6G		0x6B
#define CLR6B		0x6C
#define CLR7R		0x6D
#define CLR7G		0x6E
#define CLR7B		0x6F

// Bank =0x10  TCON bank
//Output format control
#define OFC1		0x02
#define OFC2		0x03
// output drive/polarity control
#define ODPC		0x04
#define ODC		0x05
// input format control
#define IFCTRL		0x07

//GPO0(OPOL)
#define G0VST_L		0x08
#define G0VST_H		0x09
#define G0VEND_L	0x0A
#define G0VEND_H	0x0B
#define G0HST_L		0x0C
#define G0HST_H		0x0D
#define G0HEND_L	0x0E
#define G0HEND_H	0x0F
#define G0CTRL		0x10

//GPO1(EPOL)
#define G1VST_L		0x11
#define G1VST_H		0x12
#define G1VEND_L	0x13
#define G1VEND_H	0x14
#define G1HST_L		0x15
#define G1HST_H		0x16
#define G1HEND_L	0x17
#define G1HEND_H	0x18
#define G1CTRL		0x19

//GPO2(RSP2)
#define G2VST_L		0x1A
#define G2VST_H		0x1B
#define G2VEND_L	0x1C
#define G2VEND_H	0x1D
#define G2HST_L		0x1E
#define G2HST_H		0x1F
#define G2HEND_L	0x20
#define G2HEND_H	0x21
#define G2CTRL		0x22

//GPO3(RSP3)
#define G3VST_L		0x23
#define G3VST_H		0x24
#define G3VEND_L	0x25
#define G3VEND_H	0x26
#define G3HST_L		0x27
#define G3HST_H		0x28
#define G3HEND_L	0x29
#define G3HEND_H	0x2A
#define G3CTRL		0x2B

//GPO4(RCLK)
#define G4VST_L		0x2C
#define G4VST_H		0x2D
#define G4VEND_L	0x2E
#define G4VEND_H	0x2F
#define G4HST_L		0x30
#define G4HST_H		0x31
#define G4HEND_L	0x32
#define G4HEND_H	0x33
#define G4CTRL		0x34

//GPO5(ROE)
#define G5VST_L		0x35
#define G5VST_H		0x36
#define G5VEND_L	0x37
#define G5VEND_H	0x38
#define G5HST_L		0x39
#define G5HST_H		0x3A
#define G5HEND_L	0x3B
#define G5HEND_H	0x3C
#define G5CTRL		0x3D

//GPO6(ROE2)
#define G6VST_L		0x3E
#define G6VST_H		0x3F
#define G6VEND_L	0x40
#define G6VEND_H	0x41
#define G6HST_L		0x42
#define G6HST_H		0x43
#define G6HEND_L	0x44
#define G6HEND_H	0x45
#define G6CTRL		0x46

//GPO7(ROE3)
#define G7VST_L		0x47
#define G7VST_H		0x48
#define G7VEND_L	0x49
#define G7VEND_H	0x4A
#define G7HST_L		0x4B
#define G7HST_H		0x4C
#define G7HEND_L	0x4D
#define G7HEND_H	0x4E
#define G7CTRL		0x4F

//GPO8(DHS/TCON_LP)
#define G8VST_L		0x50
#define G8VST_H		0x51
#define G8VEND_L	0x52
#define G8VEND_H	0x53
#define G8HST_L		0x54
#define G8HST_H		0x55
#define G8HEND_L	0x56
#define G8HEND_H	0x57
#define G8CTRL		0x58

//GPO9(DVS/TCON_FSYNC)
#define G9VST_L		0x59
#define G9VST_H		0x5A
#define G9VEND_L	0x5B
#define G9VEND_H	0x5C
#define G9HST_L		0x5D
#define G9HST_H		0x5E
#define G9HEND_L	0x5F
#define G9HEND_H	0x60
#define G9CTRL		0x61

//GPOA
#define GAVST_L		0x62
#define GAVST_H		0x63
#define GAVEND_L	0x64
#define GAVEND_H	0x65
#define GAHST_L		0x66
#define GAHST_H		0x67
#define GAHEND_L	0x68
#define GAHEND_H	0x69
#define GACTRL		0x6A


// Bank = 11  PIP Bank
// Sub-Window Input image sample range
#define SSPRVST_L	0x05	// V-start
#define SSPRVST_H	0x06
#define SSPRHST_L	0x07	// H-start
#define SSPRHST_H	0x08
#define SSPRVDC_L	0x09	// V-D
#define SSPRVDC_H	0x0A
#define SSPRHDC_L	0x0B	// H-D
#define SSPRHDC_H	0x0C

// Sub-Window Display Timing
//#define SWVST_L		0x10	// V-start
//#define SWVST_H		0x11
//#define SWHST_L		0x12	// h start
//#define SWHST_H		0x13
//#define SWVEND_L	0x14	// v end
//#define SWVEND_H	0x15
//#define SWHEND_L	0x16	// h end
//#define SWHEND_H	0x17

// Sub-Window scale image window size
#define SSIHST_L	0x18
#define SSIHST_H	0x19
#define SSIVEND_L	0x1A
#define SSIVEND_H	0x1B
#define SSIHEND_L	0x1C
#define SSIHEND_H	0x1D
#define SSIVST_L	0x1E
#define SSIVST_H	0x1F

// Peaking Control
#define SPPCTRL		0x3B
#define SCORING		0x3C
#define S_CTI		0x3D
#define S_LTI		0x3E
#define S_PEAK		0x3F

#define SBLENDL		0x48
	#define SWEN		BIT6
	#define FPBEN		BIT2

// Bank = 100 MIU Bank
//Memory Configuration
#define MCFG		0x02
#define DRMCFG 		0x03
#define MTMG        0x04
#define MBW0   		0x05
#define MBW1   		0x06
#define MTM   		0x07
#define MREFRT  	0x08

// Video Input Base Address for main window
// Video Input Base Address for sub window
#define SVIPB0_L    0x40
#define SVIPB0_M    0x41
#define SVIPB0_H    0x42
#define SVIPB1_L    0x43
#define SVIPB1_M    0x44
#define SVIPB1_H    0x45
#define SVIPOF_L    0x46
#define SVIPOF_H    0x47
#define SVIPFET_L   0x48
#define SVIPFET_H   0x49
#define SVOPB0_L    0x4A
#define SVOPB0_M    0x4B
#define SVOPB0_H    0x4C
#define SVOPB1_L    0x4D
#define SVOPB1_M    0x4E
#define SVOPB1_H    0x4F
#define SVOPOF_L    0x50
#define SVOPOF_H    0x51
#define SVOPFET_L   0x52
#define SVOPFET_H   0x53

// OSD MIU Interface
#define OBC_DL		0x60
#define OBC_DH		0x61
#define OBC_AL		0x62
#define OBC_AM		0x63
#define OBC_AH		0x64
#define OBC_OFST	0x65
#define OBC_WDH		0x66
#define OBC_HGH  	0x67
    #define 	OBCT	BIT7

// OSD Write Interface
#define OCBA_L      0x80
#define OCBA_H      0x81
#define OABA_L      0x82
#define OABA_H      0x83
#define O1BFBA_L    0x84
#define O1BFBA_H    0x85
#define O4BFBA_L    0x86
#define O4BFBA_H    0x87
#define OTFBA_L		0x88
#define OTFBA_H		0x89

// OSD Display Interface
#define ODCBA_L     0x8A
#define ODCBA_H     0x8B
#define ODABA_L     0x8C
#define ODABA_H     0x8D
#define OD1BFBA_L   0x8E
#define OD1BFBA_H   0x8F
#define OD4BFBA_L   0x90
#define OD4BFBA_H   0x91
#define ODTFBA_L	0x92
#define ODTFBA_H	0x93

#endif