drvpower.c

mstar 776 开发的车载dvd

		}
	    }
    	}
#endif

        if( g_u8WakeUpOnOffFlag )
        {
            if( g_u32WakeupSystemTime < gSystemTimeCount )
            {
                g_u8WakeUpOnOffFlag = 0;
                g_u32WakeupSystemTime = 0xFFFFFF;
                MDrv_Power_ResetAndPowerUp();
            }
        }


        // Current use Timer2 for RTC function
        #if 1
//        if (gSystemTimeCount >= gWakeupSystemTime)
//            MDrv_Power_ResetAndPowerUp();
        if (gWakeupSystemTime != 0xffffffff && ((gSystemTimeCount%86400) == (gWakeupSystemTime%86400)))
        {
        	fWakeUpByOnTimer = TRUE;
        	//gWakeupSystemTime = 0xFFFFFFFF;	// shjang_070202
            MDrv_Power_ResetAndPowerUp();
        }
        #else
        if (gRTCWakeup == TRUE)
        {
            MDrv_Power_ResetAndPowerUp();
            gRTCWakeup = FALSE;
        }
        #endif
    }
}


//-------------------------------------------------------------------------------------------------
/// Power saving mode for some HW module: GE, MPEG, DEMUX or DVBPLL (Right now only MPEG is used??)
/// @param
/// @return
///
//-------------------------------------------------------------------------------------------------
void MDrv_Power_Saving_Mode(U8 u8Flag, BOOLEAN bEnable)
{
    if(bEnable)
    {
        DRVPOWER_DBG(printf("MDrv_Power_Saving_Mode(Enable):0x%02bX\n", u8Flag));

        // GE Releated
        if (u8Flag & PSM_GE)
            MDrv_Power_Set_HwClock(E_HWCLK_GE_ONOFF, POWER_DOWN);

        // MPEG Releated
        if (u8Flag & PSM_MPEG)
        {
            MDrv_Power_Set_HwClock(E_HWCLK_MVD_ONOFF, POWER_DOWN);
            MDrv_Power_Set_HwClock(E_HWCLK_MVDBOOT_ONOFF, POWER_DOWN);
            MDrv_Power_Set_HwClock(E_HWCLK_DC0_ONOFF, POWER_DOWN);
        }

        // Demux Releated
        if (u8Flag & PSM_DEMUX)
        {
            MDrv_Power_Set_HwClock(E_HWCLK_TSP_ONOFF, POWER_DOWN);
            MDrv_Power_Set_HwClock(E_HWCLK_TS0_ONOFF, POWER_DOWN);
            MDrv_Power_Set_HwClock(E_HWCLK_TSOUT_ONOFF, POWER_DOWN);
            MDrv_Power_Set_HwClock(E_HWCLK_STC0_ONOFF, POWER_DOWN);
        }

        // DVBPLL Releated
        if (u8Flag & PSM_DVBPLL)
        {
            // XBYTE[DVB_PLL_PD] &= ~0x01;
        }
    }
    else
    {
        DRVPOWER_DBG(printf("MDrv_Power_Saving_Mode(Disable):0x%02bX\n", u8Flag));

        // DVBPLL Releated
        if (u8Flag & PSM_DVBPLL)
        {
            // XBYTE[DVB_PLL_PD] |= 0x01;
        }

        // MPEG Releated
        if (u8Flag & PSM_MPEG)
        {
            MDrv_Power_Set_HwClock(E_HWCLK_MVD_ONOFF, POWER_ON);
            MDrv_Power_Set_HwClock(E_HWCLK_MVDBOOT_ONOFF, POWER_ON);
            MDrv_Power_Set_HwClock(E_HWCLK_DC0_ONOFF, POWER_ON);
        }

#if 1// kevin 071224 //(!BOOTLOADER_SYSTEM)
        // Demux Releated
        if (u8Flag & PSM_DEMUX)
        {
            U8 delayloop;
            MDrv_Power_Set_HwClock(E_HWCLK_TSP_ONOFF, POWER_ON);
            MDrv_Power_Set_HwClock(E_HWCLK_TS0_ONOFF, POWER_ON);
            MDrv_Power_Set_HwClock(E_HWCLK_TSOUT_ONOFF, POWER_ON);
            MDrv_Power_Set_HwClock(E_HWCLK_STC0_ONOFF, POWER_ON);
            for(delayloop=0; delayloop<0xFE; delayloop++)
                 _nop_();
            //kill demux //MDrv_Tsp_Initial();
        }
#endif  // #if (!BOOTLOADER_SYSTEM)

        // GE Releated
        if (u8Flag & PSM_GE)
            MDrv_Power_Set_HwClock(E_HWCLK_GE_ONOFF, POWER_ON);
    }
}


//-------------------------------------------------------------------------------------------------
/// Setting HW module clock on/off/setting.
/// @param  eModule \b IN: Specify the HW module to set.
/// @return TRUE- Success.
///         FALSE - Failure.
//-------------------------------------------------------------------------------------------------
Bool MDrv_Power_Set_HwClock (enumHwModule4ClockSetting eModule, int eValue)
{
    Bool bRet = TRUE;

    switch(eModule)
    {

    // Setting MCU HW CLock
    case E_HWCLK_MCU_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_22_H, eValue, _BIT0);
        break;
    case E_HWCLK_MCU_SETTING:
        MDrv_WriteByteMask(BK_CHIPTOP_11_L, eValue, _BIT0);
        break;

    // Setting AEON HW CLock
    case E_HWCLK_AEON_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_13_L, (eValue<<6), _BIT6);
        break;

    // Setting MIU HW CLock
    case E_HWCLK_MIU_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_12_H, (eValue<<4), _BIT4);
        break;

    // Setting TSP HW CLock
    case E_HWCLK_TSP_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_13_H, (eValue<<4), _BIT4);
        break;
    case E_HWCLK_TS0_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_13_L, eValue, _BIT0);
        break;
    case E_HWCLK_TS2_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_1D_L, eValue, _BIT0);
        break;
    case E_HWCLK_TSOUT_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_1D_L, (eValue<<4), _BIT4);
        break;

    // Setting STC0 HW CLock
    case E_HWCLK_STC0_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_13_H, (eValue<<4), _BIT4);
        break;

    // Setting MADSTC HW CLock
    case E_HWCLK_MADSTC_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_14_L, (eValue<<4), _BIT4);
        break;

    // Setting MVD HW CLock
    case E_HWCLK_MVD_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_14_H, (eValue<<4), _BIT4);
        break;
    case E_HWCLK_MVDBOOT_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_14_H, eValue, _BIT0);
        break;

    // Setting M4V HW CLock
    case E_HWCLK_M4V_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_15_L, eValue, _BIT0);
        break;

    // Setting DC0 HW CLock
    case E_HWCLK_DC0_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_15_L, (eValue<<4), _BIT4);
        break;

    // Setting DHC HW CLock
    case E_HWCLK_DHC_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_17_H, eValue, _BIT0);
        MDrv_WriteByteMask(BK_CHIPTOP_15_H, eValue, _BIT0);
        MDrv_WriteByteMask(BK_CHIPTOP_2C_L, eValue, _BIT0);
        MDrv_WriteByteMask(BK_CHIPTOP_2C_L, (eValue<<2), _BIT2);
        MDrv_WriteByteMask(BK_CHIPTOP_2C_H, eValue, _BIT0);
        MDrv_WriteByteMask(BK_CHIPTOP_2C_H, (eValue<<6), _BIT6);
        break;

    // Setting GE HW CLock
    case E_HWCLK_GE_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_15_H, (eValue<<4), _BIT4);
        break;

    // Setting GOP HW CLock
    case E_HWCLK_GOP0_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_16_L, eValue, _BIT0);
        break;
    case E_HWCLK_GOP1_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_16_L, (eValue<<4), _BIT4);
        break;
    case E_HWCLK_GOPD_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_16_H, eValue, _BIT0);
        break;

    // Setting VD HW CLock (VD/VDMCU/VD200)
    case E_HWCLK_VD_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_16_H, (eValue<<4), _BIT4);
        MDrv_WriteByteMask(BK_CHIPTOP_17_L, eValue, _BIT0);
        MDrv_WriteByteMask(BK_CHIPTOP_17_L, (eValue<<4), _BIT4);
        break;

    // Setting VE HW CLock (VE/VEDAC/VEIN)
    case E_HWCLK_VE_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_19_H, eValue, _BIT0);
        MDrv_WriteByteMask(BK_CHIPTOP_19_H, (eValue<<4), _BIT4);
        MDrv_WriteByteMask(BK_CHIPTOP_1C_L, eValue, _BIT0);
        break;

    // Setting STRLD HW CLock
    case E_HWCLK_STRLD_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_22_L, eValue, _BIT0);
        break;

    // Setting DDR HW CLock
    case E_HWCLK_DDR_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_12_H, eValue, _BIT0);
        break;

    // Setting DAC HW CLock
    case E_HWCLK_DAC_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_1A_L, eValue, _BIT0);
        break;

    // Setting USB HW CLock
    case E_HWCLK_USB_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_12_L, eValue, _BIT0);
        break;

    // Setting PCMCIA HW CLock
    case E_HWCLK_PCMCIA_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_18_H, (eValue<<4), _BIT4);
        break;

    // Setting FCIE HW CLock (Card Reader)
    case E_HWCLK_FCIE_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_1C_H, eValue, _BIT0);
        break;

    // Setting FCLK HW CLock
    case E_HWCLK_FCLK_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_1A_H, eValue, _BIT0);
        break;

    // Setting FMCLK HW CLock
    case E_HWCLK_FMCLK_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_1B_L, eValue, _BIT0);
        break;

    // Setting ODCLK HW CLock
    case E_HWCLK_ODCLK_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_1B_H, eValue, _BIT0);
        break;

    // Setting FICLKF2 HW CLock
    case E_HWCLK_FICLKF2_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_18_L, (eValue<<4),_BIT4);
        break;

    // Setting IDCLK2 HW CLock
    case E_HWCLK_IDCLK2_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_1F_H, eValue, _BIT0);
        break;

    // Setting TCK HW CLock
    case E_HWCLK_TCK_ONOFF:
        MDrv_WriteByteMask(BK_CHIPTOP_13_L, (eValue<<4), _BIT4);
        break;

    default:
        bRet = FALSE;
        break;
    }

    return bRet;
}


//-------------------------------------------------------------------------------------------------
/// Checking it it is wake up by timer.
/// @param
/// @return TRUE- Success.
///         FALSE - Failure.
//-------------------------------------------------------------------------------------------------
//lachesis 1222
BOOLEAN MDrv_Power_IsWakeUpByOnTimer(void)
{
    return (BOOLEAN)(fWakeUpByOnTimer);
}

void MDrv_ReSetTimerOnFlag()
{
     fWakeUpByOnTimer=0;
}

BOOLEAN MDrv_GetTimerOnFlag()
{
     return MDrv_Power_IsWakeUpByOnTimer();
}


void MDrv_PowerResume(void)// kevin 20070829 tempoary
{
    MDrv_WriteByte(BK_SCALER_BASE, REG_BANK_DNR);
    MDrv_WriteByteMask(BK_SC_DNR_11_H, ~_BIT3, _BIT3);

    MDrv_WriteByte(BK_SCALER_BASE, REG_BANK_VOP);
    MDrv_WriteByteMask(BK_SC_VOP_19_L, ~_BIT1, _BIT1);
    MDrv_WriteByteMask(BK_SC_VOP_1C_H, ~_BIT0, _BIT0);

    MDrv_WriteByte(BK_SCALER_BASE, REG_BANK_IP1F2);
    MDrv_WriteByteMask(BK_SC_IP1F2_03_H, _BIT7, _BIT7);
    MDrv_WriteByteMask(BK_SC_IP1F2_02_L, ~_BIT7, _BIT7);
}