addre.vhd

基于FPGA有限状态机的数据采集系统

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity addre is
port(clk		:in std_logic;
	flag		:in std_logic;
	full		:out std_logic;
	addre		:out std_logic_vector(17 downto 0));
end addre;

architecture behave of addre is
	signal count:std_logic_vector(17 downto 0);
	signal full_temp:std_logic;
	
	begin
		addre<=count;	
		full<=full_temp;	
		
		
		process(flag,clk)
		--	variable full_temp:std_logic;
		begin
			if(flag='1')then
				if(clk'event and clk='1')then
					if(count="000000000000111111")then
						count<="000000000000000000";
						full_temp<='0';
					else
						count<=count+'1';
	--					full_temp:='1';
					end if;
				end if;
				
			elsif(flag='0')then
				count<="000000000000000000";
				full_temp<='1';
			end if;
	--		full<=full_temp;
		end process;
end behave;