top.tan.rpt

来自「基于FPGA有限状态机的数据采集系统」· RPT 代码 · 共 317 行 · 第 1/5 页

Classic Timing Analyzer report for top
Wed Mar 18 22:17:34 2009
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clkin'
  6. Clock Setup: 'clk_cpu'
  7. tsu
  8. tco
  9. tpd
 10. th
 11. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                           ;
+------------------------------+-------+---------------+----------------------------------+----------------------+---------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From                 ; To                        ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+----------------------+---------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 0.254 ns                         ; change               ; com:inst|current_state.s3 ; --         ; clk_cpu  ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 19.436 ns                        ; com:inst|comb_181    ; dataram[2]                ; clkin      ; --       ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 11.908 ns                        ; clk_cpu              ; adclk                     ; --         ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; 6.495 ns                         ; datain[1]            ; com:inst|dataram[1]$latch ; --         ; clkin    ; 0            ;
; Clock Setup: 'clk_cpu'       ; N/A   ; None          ; 214.59 MHz ( period = 4.660 ns ) ; addre:inst1|count[4] ; addre:inst1|count[16]     ; clk_cpu    ; clk_cpu  ; 0            ;
; Clock Setup: 'clkin'         ; N/A   ; None          ; 214.59 MHz ( period = 4.660 ns ) ; addre:inst1|count[4] ; addre:inst1|count[16]     ; clkin      ; clkin    ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                      ;                           ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+----------------------+---------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;