clk_div.vhd

来自「基于FPGA有限状态机的数据采集系统」· VHDL 代码 · 共 40 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity clk_div is
generic(n:integer:=10);
port(clkin	:in std_logic;
	clk		:out std_logic);
end clk_div;

architecture behave of clk_div is
	signal clk_temp:std_logic;
	signal count:integer range 0 to n;
	begin
		clk<=clk_temp;
		
	process(clkin)
	begin
		if(n=1)then
			clk_temp<=clkin;
			elsif(clkin'event and clkin='1')then
				if(n=2)then
				clk_temp<=not clk_temp;
				elsif(n>2)then
					if(count=n)then
						count<=0;
						else
						count<=count+1;
					end if;
					
				if(count<n/2)then
					clk_temp<='1';
					else
					clk_temp<='0';
				end if;
			end if;
		end if;
	end process;
end behave;