com.vhd

基于FPGA有限状态机的数据采集系统

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity com is										--more state
port(clk		:in std_logic;
	rst			:in std_logic;
	full		:in std_logic;
	change		:in std_logic;
	datain		:in std_logic_vector(7 downto 0);
	flag		:out std_logic;
	ready 		:out std_logic;
	adclk		:out std_logic;
	wr_ram		:out std_logic;
	rd_ram		:out std_logic;
	st			:out integer range 0 to 3;
	dataram		:inout std_logic_vector(7 downto 0);
	dataout		:out std_logic_vector(7 downto 0);
	clk_s		:out std_logic);
end com;


architecture behave of com is
	type state is(s0,s1,s2,s3);
	signal current_state,next_state :state;
	
	begin
		
		process(clk,rst)
		begin
			if(rst='1')then
				current_state<=s0;
			elsif(clk'event and clk='1')then
				current_state<=next_state;
			end if;
		end process;
		
		process(current_state,rst,full,change)
		begin
			case current_state is
			when s0=>
				if(rst='0')then						--
					next_state<=s1;
				else
					next_state<=s0;
				end if;
			when s1=>
				if(full='0')then
					next_state<=s2;
				else
					next_state<=s1;
				end if;
			when s2=>
				if(change='0')then
					next_state<=s3;
				else
					next_state<=s2;
				end if;
			when s3=>
				if(rst='1')then
					next_state<=s0;
				else
					next_state<=s3;
				end if;
			
--				if(rst='1')then
--					next_state<=s0;
--				elsif(full='0')then
--					next_state<=s0;
--				else
--					next_state<=s3;
--				end if;
			when others=>next_state<=s0;
			end case;
		end process;
		
		process(current_state)
		begin
			case current_state is
			when s0=>
				ready<='1';adclk<='1';wr_ram<='1';rd_ram<='1';flag<='0';
				dataram<=(others=>'Z');dataout<=(others=>'Z');
				st<=0;clk_s<='0';
			when s1=>
				ready<='1';adclk<=clk;wr_ram<=clk;rd_ram<='1';flag<='1';
				dataram<=datain;dataout<=(others=>'Z');
				st<=1;clk_s<='0';
			when s2=>
				ready<='0';adclk<='1';wr_ram<='1';rd_ram<='1';flag<='0';
				dataram<=(others=>'Z');dataout<=(others=>'Z');
				st<=2;clk_s<='0';
			when s3=>
				ready<='0';adclk<='1';wr_ram<='1';rd_ram<=clk;flag<='1';
				dataout<=dataram;
				st<=3;clk_s<='1';
			when others=>null;
			end case;
		end process;
end behave;