top.tan.qmsg

来自「基于FPGA有限状态机的数据采集系统」· QMSG 代码 · 共 12 行 · 第 1/5 页

{ "Info" "ITDB_FULL_TCO_RESULT" "clkin dataram\[2\] com:inst\|comb_181 19.436 ns register " "Info: tco from clock \"clkin\" to destination pin \"dataram\[2\]\" through register \"com:inst\|comb_181\" is 19.436 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 12.923 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to source register is 12.923 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clkin'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "top.bdf" "" { Schematic "G:/TASK/DVDT_MORE/top.bdf" { { 384 96 264 400 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.935 ns) 3.126 ns clk_div:inst3\|clk_temp 2 REG LC_X8_Y8_N5 2 " "Info: 2: + IC(0.722 ns) + CELL(0.935 ns) = 3.126 ns; Loc. = LC_X8_Y8_N5; Fanout = 2; REG Node = 'clk_div:inst3\|clk_temp'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "1.657 ns" { clkin clk_div:inst3|clk_temp } "NODE_NAME" } } { "clk_div.vhd" "" { Text "G:/TASK/DVDT_MORE/clk_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.571 ns) + CELL(0.114 ns) 3.811 ns clk_select:inst2\|clk~16 3 COMB LC_X8_Y8_N8 24 " "Info: 3: + IC(0.571 ns) + CELL(0.114 ns) = 3.811 ns; Loc. = LC_X8_Y8_N8; Fanout = 24; COMB Node = 'clk_select:inst2\|clk~16'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "0.685 ns" { clk_div:inst3|clk_temp clk_select:inst2|clk~16 } "NODE_NAME" } } { "clk_select.vhd" "" { Text "G:/TASK/DVDT_MORE/clk_select.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.983 ns) + CELL(0.935 ns) 8.729 ns com:inst\|current_state.s3 4 REG LC_X8_Y10_N2 21 " "Info: 4: + IC(3.983 ns) + CELL(0.935 ns) = 8.729 ns; Loc. = LC_X8_Y10_N2; Fanout = 21; REG Node = 'com:inst\|current_state.s3'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "4.918 ns" { clk_select:inst2|clk~16 com:inst|current_state.s3 } "NODE_NAME" } } { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.080 ns) + CELL(0.114 ns) 12.923 ns com:inst\|comb_181 5 REG LC_X23_Y4_N3 8 " "Info: 5: + IC(4.080 ns) + CELL(0.114 ns) = 12.923 ns; Loc. = LC_X23_Y4_N3; Fanout = 8; REG Node = 'com:inst\|comb_181'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "4.194 ns" { com:inst|current_state.s3 com:inst|comb_181 } "NODE_NAME" } } { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.567 ns ( 27.60 % ) " "Info: Total cell delay = 3.567 ns ( 27.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.356 ns ( 72.40 % ) " "Info: Total interconnect delay = 9.356 ns ( 72.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "12.923 ns" { clkin clk_div:inst3|clk_temp clk_select:inst2|clk~16 com:inst|current_state.s3 com:inst|comb_181 } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "12.923 ns" { clkin clkin~out0 clk_div:inst3|clk_temp clk_select:inst2|clk~16 com:inst|current_state.s3 com:inst|comb_181 } { 0.000ns 0.000ns 0.722ns 0.571ns 3.983ns 4.080ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.935ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.513 ns + Longest register pin " "Info: + Longest register to pin delay is 6.513 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns com:inst\|comb_181 1 REG LC_X23_Y4_N3 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y4_N3; Fanout = 8; REG Node = 'com:inst\|comb_181'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { com:inst|comb_181 } "NODE_NAME" } } { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.439 ns) + CELL(2.074 ns) 6.513 ns dataram\[2\] 2 PIN PIN_56 0 " "Info: 2: + IC(4.439 ns) + CELL(2.074 ns) = 6.513 ns; Loc. = PIN_56; Fanout = 0; PIN Node = 'dataram\[2\]'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "6.513 ns" { com:inst|comb_181 dataram[2] } "NODE_NAME" } } { "top.bdf" "" { Schematic "G:/TASK/DVDT_MORE/top.bdf" { { 648 1112 1288 664 "dataram\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.074 ns ( 31.84 % ) " "Info: Total cell delay = 2.074 ns ( 31.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.439 ns ( 68.16 % ) " "Info: Total interconnect delay = 4.439 ns ( 68.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "6.513 ns" { com:inst|comb_181 dataram[2] } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "6.513 ns" { com:inst|comb_181 dataram[2] } { 0.000ns 4.439ns } { 0.000ns 2.074ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "12.923 ns" { clkin clk_div:inst3|clk_temp clk_select:inst2|clk~16 com:inst|current_state.s3 com:inst|comb_181 } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "12.923 ns" { clkin clkin~out0 clk_div:inst3|clk_temp clk_select:inst2|clk~16 com:inst|current_state.s3 com:inst|comb_181 } { 0.000ns 0.000ns 0.722ns 0.571ns 3.983ns 4.080ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.935ns 0.114ns } "" } } { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "6.513 ns" { com:inst|comb_181 dataram[2] } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "6.513 ns" { com:inst|comb_181 dataram[2] } { 0.000ns 4.439ns } { 0.000ns 2.074ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "clk_cpu wr_ram 11.908 ns Longest " "Info: Longest tpd from source pin \"clk_cpu\" to destination pin \"wr_ram\" is 11.908 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk_cpu 1 CLK PIN_75 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_75; Fanout = 3; CLK Node = 'clk_cpu'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_cpu } "NODE_NAME" } } { "top.bdf" "" { Schematic "G:/TASK/DVDT_MORE/top.bdf" { { 488 184 352 504 "clk_cpu" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.528 ns) + CELL(0.590 ns) 7.593 ns com:inst\|adclk~6 2 COMB LC_X8_Y8_N6 2 " "Info: 2: + IC(5.528 ns) + CELL(0.590 ns) = 7.593 ns; Loc. = LC_X8_Y8_N6; Fanout = 2; COMB Node = 'com:inst\|adclk~6'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "6.118 ns" { clk_cpu com:inst|adclk~6 } "NODE_NAME" } } { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.191 ns) + CELL(2.124 ns) 11.908 ns wr_ram 3 PIN PIN_43 0 " "Info: 3: + IC(2.191 ns) + CELL(2.124 ns) = 11.908 ns; Loc. = PIN_43; Fanout = 0; PIN Node = 'wr_ram'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "4.315 ns" { com:inst|adclk~6 wr_ram } "NODE_NAME" } } { "top.bdf" "" { Schematic "G:/TASK/DVDT_MORE/top.bdf" { { 600 1112 1288 616 "wr_ram" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.189 ns ( 35.18 % ) " "Info: Total cell delay = 4.189 ns ( 35.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.719 ns ( 64.82 % ) " "Info: Total interconnect delay = 7.719 ns ( 64.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "11.908 ns" { clk_cpu com:inst|adclk~6 wr_ram } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "11.908 ns" { clk_cpu clk_cpu~out0 com:inst|adclk~6 wr_ram } { 0.000ns 0.000ns 5.528ns 2.191ns } { 0.000ns 1.475ns 0.590ns 2.124ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "com:inst\|dataram\[1\]\$latch datain\[1\] clkin 6.495 ns register " "Info: th for register \"com:inst\|dataram\[1\]\$latch\" (data pin = \"datain\[1\]\", clock pin = \"clkin\") is 6.495 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 12.932 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to destination register is 12.932 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clkin'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "top.bdf" "" { Schematic "G:/TASK/DVDT_MORE/top.bdf" { { 384 96 264 400 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.935 ns) 3.126 ns clk_div:inst3\|clk_temp 2 REG LC_X8_Y8_N5 2 " "Info: 2: + IC(0.722 ns) + CELL(0.935 ns) = 3.126 ns; Loc. = LC_X8_Y8_N5; Fanout = 2; REG Node = 'clk_div:inst3\|clk_temp'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "1.657 ns" { clkin clk_div:inst3|clk_temp } "NODE_NAME" } } { "clk_div.vhd" "" { Text "G:/TASK/DVDT_MORE/clk_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.571 ns) + CELL(0.114 ns) 3.811 ns clk_select:inst2\|clk~16 3 COMB LC_X8_Y8_N8 24 " "Info: 3: + IC(0.571 ns) + CELL(0.114 ns) = 3.811 ns; Loc. = LC_X8_Y8_N8; Fanout = 24; COMB Node = 'clk_select:inst2\|clk~16'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "0.685 ns" { clk_div:inst3|clk_temp clk_select:inst2|clk~16 } "NODE_NAME" } } { "clk_select.vhd" "" { Text "G:/TASK/DVDT_MORE/clk_select.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.983 ns) + CELL(0.935 ns) 8.729 ns com:inst\|current_state.s3 4 REG LC_X8_Y10_N2 21 " "Info: 4: + IC(3.983 ns) + CELL(0.935 ns) = 8.729 ns; Loc. = LC_X8_Y10_N2; Fanout = 21; REG Node = 'com:inst\|current_state.s3'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "4.918 ns" { clk_select:inst2|clk~16 com:inst|current_state.s3 } "NODE_NAME" } } { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.089 ns) + CELL(0.114 ns) 12.932 ns com:inst\|dataram\[1\]\$latch 5 REG LC_X34_Y6_N9 1 " "Info: 5: + IC(4.089 ns) + CELL(0.114 ns) = 12.932 ns; Loc. = LC_X34_Y6_N9; Fanout = 1; REG Node = 'com:inst\|dataram\[1\]\$latch'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "4.203 ns" { com:inst|current_state.s3 com:inst|dataram[1]$latch } "NODE_NAME" } } { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.567 ns ( 27.58 % ) " "Info: Total cell delay = 3.567 ns ( 27.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.365 ns ( 72.42 % ) " "Info: Total interconnect delay = 9.365 ns ( 72.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "12.932 ns" { clkin clk_div:inst3|clk_temp clk_select:inst2|clk~16 com:inst|current_state.s3 com:inst|dataram[1]$latch } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "12.932 ns" { clkin clkin~out0 clk_div:inst3|clk_temp clk_select:inst2|clk~16 com:inst|current_state.s3 com:inst|dataram[1]$latch } { 0.000ns 0.000ns 0.722ns 0.571ns 3.983ns 4.089ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.935ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.437 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.437 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns datain\[1\] 1 PIN PIN_136 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_136; Fanout = 1; PIN Node = 'datain\[1\]'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { datain[1] } "NODE_NAME" } } { "top.bdf" "" { Schematic "G:/TASK/DVDT_MORE/top.bdf" { { 616 408 576 632 "datain\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.526 ns) + CELL(0.442 ns) 6.437 ns com:inst\|dataram\[1\]\$latch 2 REG LC_X34_Y6_N9 1 " "Info: 2: + IC(4.526 ns) + CELL(0.442 ns) = 6.437 ns; Loc. = LC_X34_Y6_N9; Fanout = 1; REG Node = 'com:inst\|dataram\[1\]\$latch'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "4.968 ns" { datain[1] com:inst|dataram[1]$latch } "NODE_NAME" } } { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.911 ns ( 29.69 % ) " "Info: Total cell delay = 1.911 ns ( 29.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.526 ns ( 70.31 % ) " "Info: Total interconnect delay = 4.526 ns ( 70.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "6.437 ns" { datain[1] com:inst|dataram[1]$latch } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/