top.tan.qmsg

来自「基于FPGA有限状态机的数据采集系统」· QMSG 代码 · 共 12 行 · 第 1/5 页
QMSG
12 行
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkin register addre:inst1\|count\[4\] register addre:inst1\|count\[16\] 214.59 MHz 4.66 ns Internal " "Info: Clock \"clkin\" has Internal fmax of 214.59 MHz between source register \"addre:inst1\|count\[4\]\" and destination register \"addre:inst1\|count\[16\]\" (period= 4.66 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.399 ns + Longest register register " "Info: + Longest register to register delay is 4.399 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns addre:inst1\|count\[4\] 1 REG LC_X10_Y14_N2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y14_N2; Fanout = 5; REG Node = 'addre:inst1\|count\[4\]'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { addre:inst1|count[4] } "NODE_NAME" } } { "addre.vhd" "" { Text "G:/TASK/DVDT_MORE/addre.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.255 ns) + CELL(0.432 ns) 1.687 ns addre:inst1\|Add0~294COUT1 2 COMB LC_X9_Y15_N5 2 " "Info: 2: + IC(1.255 ns) + CELL(0.432 ns) = 1.687 ns; Loc. = LC_X9_Y15_N5; Fanout = 2; COMB Node = 'addre:inst1\|Add0~294COUT1'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "1.687 ns" { addre:inst1|count[4] addre:inst1|Add0~294COUT1 } "NODE_NAME" } } { "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.767 ns addre:inst1\|Add0~292COUT1 3 COMB LC_X9_Y15_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.767 ns; Loc. = LC_X9_Y15_N6; Fanout = 2; COMB Node = 'addre:inst1\|Add0~292COUT1'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { addre:inst1|Add0~294COUT1 addre:inst1|Add0~292COUT1 } "NODE_NAME" } } { "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.847 ns addre:inst1\|Add0~290COUT1 4 COMB LC_X9_Y15_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.847 ns; Loc. = LC_X9_Y15_N7; Fanout = 2; COMB Node = 'addre:inst1\|Add0~290COUT1'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { addre:inst1|Add0~292COUT1 addre:inst1|Add0~290COUT1 } "NODE_NAME" } } { "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.927 ns addre:inst1\|Add0~288COUT1 5 COMB LC_X9_Y15_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.927 ns; Loc. = LC_X9_Y15_N8; Fanout = 2; COMB Node = 'addre:inst1\|Add0~288COUT1'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { addre:inst1|Add0~290COUT1 addre:inst1|Add0~288COUT1 } "NODE_NAME" } } { "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 2.185 ns addre:inst1\|Add0~286 6 COMB LC_X9_Y15_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 2.185 ns; Loc. = LC_X9_Y15_N9; Fanout = 6; COMB Node = 'addre:inst1\|Add0~286'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "0.258 ns" { addre:inst1|Add0~288COUT1 addre:inst1|Add0~286 } "NODE_NAME" } } { "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.321 ns addre:inst1\|Add0~276 7 COMB LC_X9_Y14_N4 4 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 2.321 ns; Loc. = LC_X9_Y14_N4; Fanout = 4; COMB Node = 'addre:inst1\|Add0~276'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { addre:inst1|Add0~286 addre:inst1|Add0~276 } "NODE_NAME" } } { "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 2.942 ns addre:inst1\|Add0~269 8 COMB LC_X9_Y14_N7 1 " "Info: 8: + IC(0.000 ns) + CELL(0.621 ns) = 2.942 ns; Loc. = LC_X9_Y14_N7; Fanout = 1; COMB Node = 'addre:inst1\|Add0~269'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "0.621 ns" { addre:inst1|Add0~276 addre:inst1|Add0~269 } "NODE_NAME" } } { "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.719 ns) + CELL(0.738 ns) 4.399 ns addre:inst1\|count\[16\] 9 REG LC_X8_Y14_N9 5 " "Info: 9: + IC(0.719 ns) + CELL(0.738 ns) = 4.399 ns; Loc. = LC_X8_Y14_N9; Fanout = 5; REG Node = 'addre:inst1\|count\[16\]'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "1.457 ns" { addre:inst1|Add0~269 addre:inst1|count[16] } "NODE_NAME" } } { "addre.vhd" "" { Text "G:/TASK/DVDT_MORE/addre.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.425 ns ( 55.13 % ) " "Info: Total cell delay = 2.425 ns ( 55.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.974 ns ( 44.87 % ) " "Info: Total interconnect delay = 1.974 ns ( 44.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "4.399 ns" { addre:inst1|count[4] addre:inst1|Add0~294COUT1 addre:inst1|Add0~292COUT1 addre:inst1|Add0~290COUT1 addre:inst1|Add0~288COUT1 addre:inst1|Add0~286 addre:inst1|Add0~276 addre:inst1|Add0~269 addre:inst1|count[16] } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "4.399 ns" { addre:inst1|count[4] addre:inst1|Add0~294COUT1 addre:inst1|Add0~292COUT1 addre:inst1|Add0~290COUT1 addre:inst1|Add0~288COUT1 addre:inst1|Add0~286 addre:inst1|Add0~276 addre:inst1|Add0~269 addre:inst1|count[16] } { 0.000ns 1.255ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.719ns } { 0.000ns 0.432ns 0.080ns 0.080ns 0.080ns 0.258ns 0.136ns 0.621ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 8.536 ns + Shortest register " "Info: + Shortest clock path from clock \"clkin\" to destination register is 8.536 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clkin'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "top.bdf" "" { Schematic "G:/TASK/DVDT_MORE/top.bdf" { { 384 96 264 400 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.935 ns) 3.126 ns clk_div:inst3\|clk_temp 2 REG LC_X8_Y8_N5 2 " "Info: 2: + IC(0.722 ns) + CELL(0.935 ns) = 3.126 ns; Loc. = LC_X8_Y8_N5; Fanout = 2; REG Node = 'clk_div:inst3\|clk_temp'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "1.657 ns" { clkin clk_div:inst3|clk_temp } "NODE_NAME" } } { "clk_div.vhd" "" { Text "G:/TASK/DVDT_MORE/clk_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.571 ns) + CELL(0.114 ns) 3.811 ns clk_select:inst2\|clk~16 3 COMB LC_X8_Y8_N8 24 " "Info: 3: + IC(0.571 ns) + CELL(0.114 ns) = 3.811 ns; Loc. = LC_X8_Y8_N8; Fanout = 24; COMB Node = 'clk_select:inst2\|clk~16'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "0.685 ns" { clk_div:inst3|clk_temp clk_select:inst2|clk~16 } "NODE_NAME" } } { "clk_select.vhd" "" { Text "G:/TASK/DVDT_MORE/clk_select.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.014 ns) + CELL(0.711 ns) 8.536 ns addre:inst1\|count\[16\] 4 REG LC_X8_Y14_N9 5 " "Info: 4: + IC(4.014 ns) + CELL(0.711 ns) = 8.536 ns; Loc. = LC_X8_Y14_N9; Fanout = 5; REG Node = 'addre:inst1\|count\[16\]'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "4.725 ns" { clk_select:inst2|clk~16 addre:inst1|count[16] } "NODE_NAME" } } { "addre.vhd" "" { Text "G:/TASK/DVDT_MORE/addre.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.229 ns ( 37.83 % ) " "Info: Total cell delay = 3.229 ns ( 37.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.307 ns ( 62.17 % ) " "Info: Total interconnect delay = 5.307 ns ( 62.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "8.536 ns" { clkin clk_div:inst3|clk_temp clk_select:inst2|clk~16 addre:inst1|count[16] } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "8.536 ns" { clkin clkin~out0 clk_div:inst3|clk_temp clk_select:inst2|clk~16 addre:inst1|count[16] } { 0.000ns 0.000ns 0.722ns 0.571ns 4.014ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 8.536 ns - Longest register " "Info: - Longest clock path from clock \"clkin\" to source register is 8.536 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clkin'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "top.bdf" "" { Schematic "G:/TASK/DVDT_MORE/top.bdf" { { 384 96 264 400 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.935 ns) 3.126 ns clk_div:inst3\|clk_temp 2 REG LC_X8_Y8_N5 2 " "Info: 2: + IC(0.722 ns) + CELL(0.935 ns) = 3.126 ns; Loc. = LC_X8_Y8_N5; Fanout = 2; REG Node = 'clk_div:inst3\|clk_temp'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "1.657 ns" { clkin clk_div:inst3|clk_temp } "NODE_NAME" } } { "clk_div.vhd" "" { Text "G:/TASK/DVDT_MORE/clk_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.571 ns) + CELL(0.114 ns) 3.811 ns clk_select:inst2\|clk~16 3 COMB LC_X8_Y8_N8 24 " "Info: 3: + IC(0.571 ns) + CELL(0.114 ns) = 3.811 ns; Loc. = LC_X8_Y8_N8; Fanout = 24; COMB Node = 'clk_select:inst2\|clk~16'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "0.685 ns" { clk_div:inst3|clk_temp clk_select:inst2|clk~16 } "NODE_NAME" } } { "clk_select.vhd" "" { Text "G:/TASK/DVDT_MORE/clk_select.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.014 ns) + CELL(0.711 ns) 8.536 ns addre:inst1\|count\[4\] 4 REG LC_X10_Y14_N2 5 " "Info: 4: + IC(4.014 ns) + CELL(0.711 ns) = 8.536 ns; Loc. = LC_X10_Y14_N2; Fanout = 5; REG Node = 'addre:inst1\|count\[4\]'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "4.725 ns" { clk_select:inst2|clk~16 addre:inst1|count[4] } "NODE_NAME" } } { "addre.vhd" "" { Text "G:/TASK/DVDT_MORE/addre.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.229 ns ( 37.83 % ) " "Info: Total cell delay = 3.229 ns ( 37.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.307 ns ( 62.17 % ) " "Info: Total interconnect delay = 5.307 ns ( 62.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "8.536 ns" { clkin clk_div:inst3|clk_temp clk_select:inst2|clk~16 addre:inst1|count[4] } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "8.536 ns" { clkin clkin~out0 clk_div:inst3|clk_temp clk_select:inst2|clk~16 addre:inst1|count[4] } { 0.000ns 0.000ns 0.722ns 0.571ns 4.014ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "8.536 ns" { clkin clk_div:inst3|clk_temp clk_select:inst2|clk~16 addre:inst1|count[16] } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "8.536 ns" { clkin clkin~out0 clk_div:inst3|clk_temp clk_select:inst2|clk~16 addre:inst1|count[16] } { 0.000ns 0.000ns 0.722ns 0.571ns 4.014ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.711ns } "" } } { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "8.536 ns" { clkin clk_div:inst3|clk_temp clk_select:inst2|clk~16 addre:inst1|count[4] } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "8.536 ns" { clkin clkin~out0 clk_div:inst3|clk_temp clk_select:inst2|clk~16 addre:inst1|count[4] } { 0.000ns 0.000ns 0.722ns 0.571ns 4.014ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "addre.vhd" "" { Text "G:/TASK/DVDT_MORE/addre.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "addre.vhd" "" { Text "G:/TASK/DVDT_MORE/addre.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "4.399 ns" { addre:inst1|count[4] addre:inst1|Add0~294COUT1 addre:inst1|Add0~292COUT1 addre:inst1|Add0~290COUT1 addre:inst1|Add0~288COUT1 addre:inst1|Add0~286 addre:inst1|Add0~276 addre:inst1|Add0~269 addre:inst1|count[16] } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "4.399 ns" { addre:inst1|count[4] addre:inst1|Add0~294COUT1 addre:inst1|Add0~292COUT1 addre:inst1|Add0~290COUT1 addre:inst1|Add0~288COUT1 addre:inst1|Add0~286 addre:inst1|Add0~276 addre:inst1|Add0~269 addre:inst1|count[16] } { 0.000ns 1.255ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.719ns } { 0.000ns 0.432ns 0.080ns 0.080ns 0.080ns 0.258ns 0.136ns 0.621ns 0.738ns } "" } } { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "8.536 ns" { clkin clk_div:inst3|clk_temp clk_select:inst2|clk~16 addre:inst1|count[16] } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "8.536 ns" { clkin clkin~out0 clk_div:inst3|clk_temp clk_select:inst2|clk~16 addre:inst1|count[16] } { 0.000ns 0.000ns 0.722ns 0.571ns 4.014ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.711ns } "" } } { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "8.536 ns" { clkin clk_div:inst3|clk_temp clk_select:inst2|clk~16 addre:inst1|count[4] } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "8.536 ns" { clkin clkin~out0 clk_div:inst3|clk_temp clk_select:inst2|clk~16 addre:inst1|count[4] } { 0.000ns 0.000ns 0.722ns 0.571ns 4.014ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_cpu register addre:inst1\|count\[4\] register addre:inst1\|count\[16\] 214.59 MHz 4.66 ns Internal " "Info: Clock \"clk_cpu\" has Internal fmax of 214.59 MHz between source register \"addre:inst1\|count\[4\]\" and destination register \"addre:inst1\|count\[16\]\" (period= 4.66 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.399 ns + Longest register register " "Info: + Longest register to register delay is 4.399 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns addre:inst1\|count\[4\] 1 REG LC_X10_Y14_N2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y14_N2; Fanout = 5; REG Node = 'addre:inst1\|count\[4\]'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { addre:inst1|count[4] } "NODE_NAME" } } { "addre.vhd" "" { Text "G:/TASK/DVDT_MORE/addre.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.255 ns) + CELL(0.432 ns) 1.687 ns addre:inst1\|Add0~294COUT1 2 COMB LC_X9_Y15_N5 2 " "Info: 2: + IC(1.255 ns) + CELL(0.432 ns) = 1.687 ns; Loc. = LC_X9_Y15_N5; Fanout = 2; COMB Node = 'addre:inst1\|Add0~294COUT1'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "1.687 ns" { addre:inst1|count[4] addre:inst1|Add0~294COUT1 } "NODE_NAME" } } { "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.767 ns addre:inst1\|Add0~292COUT1 3 COMB LC_X9_Y15_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.767 ns; Loc. = LC_X9_Y15_N6; Fanout = 2; COMB Node = 'addre:inst1\|Add0~292COUT1'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { addre:inst1|Add0~294COUT1 addre:inst1|Add0~292COUT1 } "NODE_NAME" } } { "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.847 ns addre:inst1\|Add0~290COUT1 4 COMB LC_X9_Y15_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.847 ns; Loc. = LC_X9_Y15_N7; Fanout = 2; COMB Node = 'addre:inst1\|Add0~290COUT1'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { addre:inst1|Add0~292COUT1 addre:inst1|Add0~290COUT1 } "NODE_NAME" } } { "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.927 ns addre:inst1\|Add0~288COUT1 5 COMB LC_X9_Y15_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.927 ns; Loc. = LC_X9_Y15_N8; Fanout = 2; COMB Node = 'addre:inst1\|Add0~288COUT1'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { addre:inst1|Add0~290COUT1 addre:inst1|Add0~288COUT1 } "NODE_NAME" } } { "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 2.185 ns addre:inst1\|Add0~286 6 COMB LC_X9_Y15_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 2.185 ns; Loc. = LC_X9_Y15_N9; Fanout = 6; COMB Node = 'addre:inst1\|Add0~286'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "0.258 ns" { addre:inst1|Add0~288COUT1 addre:inst1|Add0~286 } "NODE_NAME" } } { "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.321 ns addre:inst1\|Add0~276 7 COMB LC_X9_Y14_N4 4 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 2.321 ns; Loc. = LC_X9_Y14_N4; Fanout = 4; COMB Node = 'addre:inst1\|Add0~276'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { addre:inst1|Add0~286 addre:inst1|Add0~276 } "NODE_NAME" } } { "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 2.942 ns addre:inst1\|Add0~269 8 COMB LC_X9_Y14_N7 1 " "Info: 8: + IC(0.000 ns) + CELL(0.621 ns) = 2.942 ns; Loc. = LC_X9_Y14_N7; Fanout = 1; COMB Node = 'addre:inst1\|Add0~269'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "0.621 ns" { addre:inst1|Add0~276 addre:inst1|Add0~269 } "NODE_NAME" } } { "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.719 ns) + CELL(0.738 ns) 4.399 ns addre:inst1\|count\[16\] 9 REG LC_X8_Y14_N9 5 " "Info: 9: + IC(0.719 ns) + CELL(0.738 ns) = 4.399 ns; Loc. = LC_X8_Y14_N9; Fanout = 5; REG Node = 'addre:inst1\|count\[16\]'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "1.457 ns" { addre:inst1|Add0~269 addre:inst1|count[16] } "NODE_NAME" } } { "addre.vhd" "" { Text "G:/TASK/DVDT_MORE/addre.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.425 ns ( 55.13 % ) " "Info: Total cell delay = 2.425 ns ( 55.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.974 ns ( 44.87 % ) " "Info: Total interconnect delay = 1.974 ns ( 44.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "4.399 ns" { addre:inst1|count[4] addre:inst1|Add0~294COUT1 addre:inst1|Add0~292COUT1 addre:inst1|Add0~290COUT1 addre:inst1|Add0~288COUT1 addre:inst1|Add0~286 addre:inst1|Add0~276 addre:inst1|Add0~269 addre:inst1|count[16] } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "4.399 ns" { addre:inst1|count[4] addre:inst1|Add0~294COUT1 addre:inst1|Add0~292COUT1 addre:inst1|Add0~290COUT1 addre:inst1|Add0~288COUT1 addre:inst1|Add0~286 addre:inst1|Add0~276 addre:inst1|Add0~269 addre:inst1|count[16] } { 0.000ns 1.255ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.719ns } { 0.000ns 0.432ns 0.080ns 0.080ns 0.080ns 0.258ns 0.136ns 0.621ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_cpu destination 8.243 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_cpu\" to destination register is 8.243 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk_cpu 1 CLK PIN_75 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_75; Fanout = 3; CLK Node = 'clk_cpu'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_cpu } "NODE_NAME" } } { "top.bdf" "" { Schematic "G:/TASK/DVDT_MORE/top.bdf" { { 488 184 352 504 "clk_cpu" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.751 ns) + CELL(0.292 ns) 3.518 ns clk_select:inst2\|clk~16 2 COMB LC_X8_Y8_N8 24 " "Info: 2: + IC(1.751 ns) + CELL(0.292 ns) = 3.518 ns; Loc. = LC_X8_Y8_N8; Fanout = 24; COMB Node = 'clk_select:inst2\|clk~16'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "2.043 ns" { clk_cpu clk_select:inst2|clk~16 } "NODE_NAME" } } { "clk_select.vhd" "" { Text "G:/TASK/DVDT_MORE/clk_select.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.014 ns) + CELL(0.711 ns) 8.243 ns addre:inst1\|count\[16\] 3 REG LC_X8_Y14_N9 5 " "Info: 3: + IC(4.014 ns) + CELL(0.711 ns) = 8.243 ns; Loc. = LC_X8_Y14_N9; Fanout = 5; REG Node = 'addre:inst1\|count\[16\]'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "4.725 ns" { clk_select:inst2|clk~16 addre:inst1|count[16] } "NODE_NAME" } } { "addre.vhd" "" { Text "G:/TASK/DVDT_MORE/addre.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.478 ns ( 30.06 % ) " "Info: Total cell delay = 2.478 ns ( 30.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.765 ns ( 69.94 % ) " "Info: Total interconnect delay = 5.765 ns ( 69.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "8.243 ns" { clk_cpu clk_select:inst2|clk~16 addre:inst1|count[16] } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "8.243 ns" { clk_cpu clk_cpu~out0 clk_select:inst2|clk~16 addre:inst1|count[16] } { 0.000ns 0.000ns 1.751ns 4.014ns } { 0.000ns 1.475ns 0.292ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_cpu source 8.243 ns - Longest register " "Info: - Longest clock path from clock \"clk_cpu\" to source register is 8.243 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk_cpu 1 CLK PIN_75 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_75; Fanout = 3; CLK Node = 'clk_cpu'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_cpu } "NODE_NAME" } } { "top.bdf" "" { Schematic "G:/TASK/DVDT_MORE/top.bdf" { { 488 184 352 504 "clk_cpu" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.751 ns) + CELL(0.292 ns) 3.518 ns clk_select:inst2\|clk~16 2 COMB LC_X8_Y8_N8 24 " "Info: 2: + IC(1.751 ns) + CELL(0.292 ns) = 3.518 ns; Loc. = LC_X8_Y8_N8; Fanout = 24; COMB Node = 'clk_select:inst2\|clk~16'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "2.043 ns" { clk_cpu clk_select:inst2|clk~16 } "NODE_NAME" } } { "clk_select.vhd" "" { Text "G:/TASK/DVDT_MORE/clk_select.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.014 ns) + CELL(0.711 ns) 8.243 ns addre:inst1\|count\[4\] 3 REG LC_X10_Y14_N2 5 " "Info: 3: + IC(4.014 ns) + CELL(0.711 ns) = 8.243 ns; Loc. = LC_X10_Y14_N2; Fanout = 5; REG Node = 'addre:inst1\|count\[4\]'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "4.725 ns" { clk_select:inst2|clk~16 addre:inst1|count[4] } "NODE_NAME" } } { "addre.vhd" "" { Text "G:/TASK/DVDT_MORE/addre.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.478 ns ( 30.06 % ) " "Info: Total cell delay = 2.478 ns ( 30.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.765 ns ( 69.94 % ) " "Info: Total interconnect delay = 5.765 ns ( 69.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "8.243 ns" { clk_cpu clk_select:inst2|clk~16 addre:inst1|count[4] } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "8.243 ns" { clk_cpu clk_cpu~out0 clk_select:inst2|clk~16 addre:inst1|count[4] } { 0.000ns 0.000ns 1.751ns 4.014ns } { 0.000ns 1.475ns 0.292ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "8.243 ns" { clk_cpu clk_select:inst2|clk~16 addre:inst1|count[16] } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "8.243 ns" { clk_cpu clk_cpu~out0 clk_select:inst2|clk~16 addre:inst1|count[16] } { 0.000ns 0.000ns 1.751ns 4.014ns } { 0.000ns 1.475ns 0.292ns 0.711ns } "" } } { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "8.243 ns" { clk_cpu clk_select:inst2|clk~16 addre:inst1|count[4] } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "8.243 ns" { clk_cpu clk_cpu~out0 clk_select:inst2|clk~16 addre:inst1|count[4] } { 0.000ns 0.000ns 1.751ns 4.014ns } { 0.000ns 1.475ns 0.292ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "addre.vhd" "" { Text "G:/TASK/DVDT_MORE/addre.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "addre.vhd" "" { Text "G:/TASK/DVDT_MORE/addre.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "4.399 ns" { addre:inst1|count[4] addre:inst1|Add0~294COUT1 addre:inst1|Add0~292COUT1 addre:inst1|Add0~290COUT1 addre:inst1|Add0~288COUT1 addre:inst1|Add0~286 addre:inst1|Add0~276 addre:inst1|Add0~269 addre:inst1|count[16] } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "4.399 ns" { addre:inst1|count[4] addre:inst1|Add0~294COUT1 addre:inst1|Add0~292COUT1 addre:inst1|Add0~290COUT1 addre:inst1|Add0~288COUT1 addre:inst1|Add0~286 addre:inst1|Add0~276 addre:inst1|Add0~269 addre:inst1|count[16] } { 0.000ns 1.255ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.719ns } { 0.000ns 0.432ns 0.080ns 0.080ns 0.080ns 0.258ns 0.136ns 0.621ns 0.738ns } "" } } { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "8.243 ns" { clk_cpu clk_select:inst2|clk~16 addre:inst1|count[16] } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "8.243 ns" { clk_cpu clk_cpu~out0 clk_select:inst2|clk~16 addre:inst1|count[16] } { 0.000ns 0.000ns 1.751ns 4.014ns } { 0.000ns 1.475ns 0.292ns 0.711ns } "" } } { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "8.243 ns" { clk_cpu clk_select:inst2|clk~16 addre:inst1|count[4] } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "8.243 ns" { clk_cpu clk_cpu~out0 clk_select:inst2|clk~16 addre:inst1|count[4] } { 0.000ns 0.000ns 1.751ns 4.014ns } { 0.000ns 1.475ns 0.292ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "com:inst\|current_state.s3 change clk_cpu 0.254 ns register " "Info: tsu for register \"com:inst\|current_state.s3\" (data pin = \"change\", clock pin = \"clk_cpu\") is 0.254 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.429 ns + Longest pin register " "Info: + Longest pin to register delay is 8.429 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns change 1 PIN PIN_67 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_67; Fanout = 2; PIN Node = 'change'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { change } "NODE_NAME" } } { "top.bdf" "" { Schematic "G:/TASK/DVDT_MORE/top.bdf" { { 600 408 576 616 "change" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.216 ns) + CELL(0.738 ns) 8.429 ns com:inst\|current_state.s3 2 REG LC_X8_Y10_N2 21 " "Info: 2: + IC(6.216 ns) + CELL(0.738 ns) = 8.429 ns; Loc. = LC_X8_Y10_N2; Fanout = 21; REG Node = 'com:inst\|current_state.s3'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "6.954 ns" { change com:inst|current_state.s3 } "NODE_NAME" } } { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.213 ns ( 26.25 % ) " "Info: Total cell delay = 2.213 ns ( 26.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.216 ns ( 73.75 % ) " "Info: Total interconnect delay = 6.216 ns ( 73.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "8.429 ns" { change com:inst|current_state.s3 } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "8.429 ns" { change change~out0 com:inst|current_state.s3 } { 0.000ns 0.000ns 6.216ns } { 0.000ns 1.475ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_cpu destination 8.212 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_cpu\" to destination register is 8.212 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk_cpu 1 CLK PIN_75 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_75; Fanout = 3; CLK Node = 'clk_cpu'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_cpu } "NODE_NAME" } } { "top.bdf" "" { Schematic "G:/TASK/DVDT_MORE/top.bdf" { { 488 184 352 504 "clk_cpu" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.751 ns) + CELL(0.292 ns) 3.518 ns clk_select:inst2\|clk~16 2 COMB LC_X8_Y8_N8 24 " "Info: 2: + IC(1.751 ns) + CELL(0.292 ns) = 3.518 ns; Loc. = LC_X8_Y8_N8; Fanout = 24; COMB Node = 'clk_select:inst2\|clk~16'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "2.043 ns" { clk_cpu clk_select:inst2|clk~16 } "NODE_NAME" } } { "clk_select.vhd" "" { Text "G:/TASK/DVDT_MORE/clk_select.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.983 ns) + CELL(0.711 ns) 8.212 ns com:inst\|current_state.s3 3 REG LC_X8_Y10_N2 21 " "Info: 3: + IC(3.983 ns) + CELL(0.711 ns) = 8.212 ns; Loc. = LC_X8_Y10_N2; Fanout = 21; REG Node = 'com:inst\|current_state.s3'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "4.694 ns" { clk_select:inst2|clk~16 com:inst|current_state.s3 } "NODE_NAME" } } { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.478 ns ( 30.18 % ) " "Info: Total cell delay = 2.478 ns ( 30.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.734 ns ( 69.82 % ) " "Info: Total interconnect delay = 5.734 ns ( 69.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "8.212 ns" { clk_cpu clk_select:inst2|clk~16 com:inst|current_state.s3 } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "8.212 ns" { clk_cpu clk_cpu~out0 clk_select:inst2|clk~16 com:inst|current_state.s3 } { 0.000ns 0.000ns 1.751ns 3.983ns } { 0.000ns 1.475ns 0.292ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "8.429 ns" { change com:inst|current_state.s3 } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "8.429 ns" { change change~out0 com:inst|current_state.s3 } { 0.000ns 0.000ns 6.216ns } { 0.000ns 1.475ns 0.738ns } "" } } { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "8.212 ns" { clk_cpu clk_select:inst2|clk~16 com:inst|current_state.s3 } "NODE_NAME" } } { "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/quartus/bin/Technology_Viewer.qrui" "8.212 ns" { clk_cpu clk_cpu~out0 clk_select:inst2|clk~16 com:inst|current_state.s3 } { 0.000ns 0.000ns 1.751ns 3.983ns } { 0.000ns 1.475ns 0.292ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
top.tan.qmsg - 源码说明

本页面展示了「基于FPGA有限状态机的数据采集系统」中的 top.tan.qmsg 源码文件，采用 QMSG 编程语言编写，共 12 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。
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