top.tan.qmsg

来自「基于FPGA有限状态机的数据采集系统」· QMSG 代码 · 共 12 行 · 第 1/5 页

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "com:inst\|dataram\[7\]\$latch " "Warning: Node \"com:inst\|dataram\[7\]\$latch\" is a latch" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "com:inst\|comb_181 " "Warning: Node \"com:inst\|comb_181\" is a latch" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "com:inst\|dataram\[6\]\$latch " "Warning: Node \"com:inst\|dataram\[6\]\$latch\" is a latch" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "com:inst\|dataram\[5\]\$latch " "Warning: Node \"com:inst\|dataram\[5\]\$latch\" is a latch" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "com:inst\|dataram\[4\]\$latch " "Warning: Node \"com:inst\|dataram\[4\]\$latch\" is a latch" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "com:inst\|dataram\[3\]\$latch " "Warning: Node \"com:inst\|dataram\[3\]\$latch\" is a latch" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "com:inst\|dataram\[2\]\$latch " "Warning: Node \"com:inst\|dataram\[2\]\$latch\" is a latch" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "com:inst\|dataram\[1\]\$latch " "Warning: Node \"com:inst\|dataram\[1\]\$latch\" is a latch" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "com:inst\|dataram\[0\]\$latch " "Warning: Node \"com:inst\|dataram\[0\]\$latch\" is a latch" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clkin " "Info: Assuming node \"clkin\" is an undefined clock" {  } { { "top.bdf" "" { Schematic "G:/TASK/DVDT_MORE/top.bdf" { { 384 96 264 400 "clkin" "" } } } } { "g:/quartus ii/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/quartus ii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkin" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_cpu " "Info: Assuming node \"clk_cpu\" is an undefined clock" {  } { { "top.bdf" "" { Schematic "G:/TASK/DVDT_MORE/top.bdf" { { 488 184 352 504 "clk_cpu" "" } } } } { "g:/quartus ii/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/quartus ii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_cpu" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk_div:inst3\|clk_temp " "Info: Detected ripple clock \"clk_div:inst3\|clk_temp\" as buffer" {  } { { "clk_div.vhd" "" { Text "G:/TASK/DVDT_MORE/clk_div.vhd" 20 -1 0 } } { "g:/quartus ii/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/quartus ii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_div:inst3\|clk_temp" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "com:inst\|current_state.s3 " "Info: Detected ripple clock \"com:inst\|current_state.s3\" as buffer" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 27 -1 0 } } { "g:/quartus ii/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/quartus ii/quartus/bin/Assignment Editor.qase" 1 { { 0 "com:inst\|current_state.s3" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "clk_select:inst2\|clk~16 " "Info: Detected gated clock \"clk_select:inst2\|clk~16\" as buffer" {  } { { "clk_select.vhd" "" { Text "G:/TASK/DVDT_MORE/clk_select.vhd" 8 -1 0 } } { "g:/quartus ii/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/quartus ii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_select:inst2\|clk~16" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}