top.map.qmsg

基于FPGA有限状态机的数据采集系统

{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "dataram com.vhd(79) " "Warning (10631): VHDL Process Statement warning at com.vhd(79): inferring latch(es) for signal or variable \"dataram\", which holds its previous value in one or more paths through the process" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "dataram\[0\] com.vhd(79) " "Info (10041): Verilog HDL or VHDL info at com.vhd(79): inferred latch for \"dataram\[0\]\"" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "dataram\[1\] com.vhd(79) " "Info (10041): Verilog HDL or VHDL info at com.vhd(79): inferred latch for \"dataram\[1\]\"" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "dataram\[2\] com.vhd(79) " "Info (10041): Verilog HDL or VHDL info at com.vhd(79): inferred latch for \"dataram\[2\]\"" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "dataram\[3\] com.vhd(79) " "Info (10041): Verilog HDL or VHDL info at com.vhd(79): inferred latch for \"dataram\[3\]\"" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "dataram\[4\] com.vhd(79) " "Info (10041): Verilog HDL or VHDL info at com.vhd(79): inferred latch for \"dataram\[4\]\"" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "dataram\[5\] com.vhd(79) " "Info (10041): Verilog HDL or VHDL info at com.vhd(79): inferred latch for \"dataram\[5\]\"" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "dataram\[6\] com.vhd(79) " "Info (10041): Verilog HDL or VHDL info at com.vhd(79): inferred latch for \"dataram\[6\]\"" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "dataram\[7\] com.vhd(79) " "Info (10041): Verilog HDL or VHDL info at com.vhd(79): inferred latch for \"dataram\[7\]\"" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 79 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|top\|com:inst\|current_state 4 " "Info: State machine \"\|top\|com:inst\|current_state\" contains 4 states" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 27 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|top\|com:inst\|current_state " "Info: Selected Auto state machine encoding method for state machine \"\|top\|com:inst\|current_state\"" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 27 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|top\|com:inst\|current_state " "Info: Encoding result for state machine \"\|top\|com:inst\|current_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "com:inst\|current_state.s3 " "Info: Encoded state bit \"com:inst\|current_state.s3\"" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "com:inst\|current_state.s2 " "Info: Encoded state bit \"com:inst\|current_state.s2\"" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "com:inst\|current_state.s1 " "Info: Encoded state bit \"com:inst\|current_state.s1\"" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "com:inst\|current_state.s0 " "Info: Encoded state bit \"com:inst\|current_state.s0\"" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|com:inst\|current_state.s0 0000 " "Info: State \"\|top\|com:inst\|current_state.s0\" uses code string \"0000\"" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|com:inst\|current_state.s1 0011 " "Info: State \"\|top\|com:inst\|current_state.s1\" uses code string \"0011\"" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|com:inst\|current_state.s2 0101 " "Info: State \"\|top\|com:inst\|current_state.s2\" uses code string \"0101\"" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|com:inst\|current_state.s3 1001 " "Info: State \"\|top\|com:inst\|current_state.s3\" uses code string \"1001\"" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 27 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "addre.vhd" "" { Text "G:/TASK/DVDT_MORE/addre.vhd" 25 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "140 " "Info: Implemented 140 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "42 " "Info: Implemented 42 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "16 " "Info: Implemented 16 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "70 " "Info: Implemented 70 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "139 " "Info: Allocated 139 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 18 22:17:17 2009 " "Info: Processing ended: Wed Mar 18 22:17:17 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}