top.map.qmsg

基于FPGA有限状态机的数据采集系统

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 18 22:17:15 2009 " "Info: Processing started: Wed Mar 18 22:17:15 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off top -c top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "com.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file com.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 com-behave " "Info: Found design unit 1: com-behave" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 25 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 com " "Info: Found entity 1: com" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "addre.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file addre.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 addre-behave " "Info: Found design unit 1: addre-behave" {  } { { "addre.vhd" "" { Text "G:/TASK/DVDT_MORE/addre.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 addre " "Info: Found entity 1: addre" {  } { { "addre.vhd" "" { Text "G:/TASK/DVDT_MORE/addre.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file top.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Info: Found entity 1: top" {  } { { "top.bdf" "" { Schematic "G:/TASK/DVDT_MORE/top.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_select.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clk_select.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clk_select-behave " "Info: Found design unit 1: clk_select-behave" {  } { { "clk_select.vhd" "" { Text "G:/TASK/DVDT_MORE/clk_select.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clk_select " "Info: Found entity 1: clk_select" {  } { { "clk_select.vhd" "" { Text "G:/TASK/DVDT_MORE/clk_select.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "top " "Info: Elaborating entity \"top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addre addre:inst1 " "Info: Elaborating entity \"addre\" for hierarchy \"addre:inst1\"" {  } { { "top.bdf" "inst1" { Schematic "G:/TASK/DVDT_MORE/top.bdf" { { 448 896 1024 544 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_select clk_select:inst2 " "Info: Elaborating entity \"clk_select\" for hierarchy \"clk_select:inst2\"" {  } { { "top.bdf" "inst2" { Schematic "G:/TASK/DVDT_MORE/top.bdf" { { 448 464 560 544 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "clk_div.vhd 2 1 " "Warning: Using design file clk_div.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clk_div-behave " "Info: Found design unit 1: clk_div-behave" {  } { { "clk_div.vhd" "" { Text "G:/TASK/DVDT_MORE/clk_div.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clk_div " "Info: Found entity 1: clk_div" {  } { { "clk_div.vhd" "" { Text "G:/TASK/DVDT_MORE/clk_div.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_div clk_div:inst3 " "Info: Elaborating entity \"clk_div\" for hierarchy \"clk_div:inst3\"" {  } { { "top.bdf" "inst3" { Schematic "G:/TASK/DVDT_MORE/top.bdf" { { 360 304 400 456 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "com com:inst " "Info: Elaborating entity \"com\" for hierarchy \"com:inst\"" {  } { { "top.bdf" "inst" { Schematic "G:/TASK/DVDT_MORE/top.bdf" { { 528 632 808 720 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk com.vhd(87) " "Warning (10492): VHDL Process Statement warning at com.vhd(87): signal \"clk\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 87 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "datain com.vhd(88) " "Warning (10492): VHDL Process Statement warning at com.vhd(88): signal \"datain\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 88 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk com.vhd(95) " "Warning (10492): VHDL Process Statement warning at com.vhd(95): signal \"clk\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 95 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "dataram com.vhd(96) " "Warning (10492): VHDL Process Statement warning at com.vhd(96): signal \"dataram\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "com.vhd" "" { Text "G:/TASK/DVDT_MORE/com.vhd" 96 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}