top.fit.qmsg

来自「基于FPGA有限状态机的数据采集系统」· QMSG 代码 · 共 48 行 · 第 1/5 页

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.593 ns register register " "Info: Estimated most critical path is register to register delay of 4.593 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns addre:inst1\|count\[4\] 1 REG LAB_X10_Y14 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X10_Y14; Fanout = 5; REG Node = 'addre:inst1\|count\[4\]'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { addre:inst1|count[4] } "NODE_NAME" } } { "addre.vhd" "" { Text "G:/TASK/DVDT_MORE/addre.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.141 ns) + CELL(0.575 ns) 1.716 ns addre:inst1\|Add0~294COUT1 2 COMB LAB_X9_Y15 2 " "Info: 2: + IC(1.141 ns) + CELL(0.575 ns) = 1.716 ns; Loc. = LAB_X9_Y15; Fanout = 2; COMB Node = 'addre:inst1\|Add0~294COUT1'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "1.716 ns" { addre:inst1|count[4] addre:inst1|Add0~294COUT1 } "NODE_NAME" } } { "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.796 ns addre:inst1\|Add0~292COUT1 3 COMB LAB_X9_Y15 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.796 ns; Loc. = LAB_X9_Y15; Fanout = 2; COMB Node = 'addre:inst1\|Add0~292COUT1'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { addre:inst1|Add0~294COUT1 addre:inst1|Add0~292COUT1 } "NODE_NAME" } } { "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 2.404 ns addre:inst1\|Add0~289 4 COMB LAB_X9_Y15 1 " "Info: 4: + IC(0.000 ns) + CELL(0.608 ns) = 2.404 ns; Loc. = LAB_X9_Y15; Fanout = 1; COMB Node = 'addre:inst1\|Add0~289'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "0.608 ns" { addre:inst1|Add0~292COUT1 addre:inst1|Add0~289 } "NODE_NAME" } } { "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus ii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.590 ns) 3.739 ns addre:inst1\|count~200 5 COMB LAB_X8_Y14 1 " "Info: 5: + IC(0.745 ns) + CELL(0.590 ns) = 3.739 ns; Loc. = LAB_X8_Y14; Fanout = 1; COMB Node = 'addre:inst1\|count~200'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "1.335 ns" { addre:inst1|Add0~289 addre:inst1|count~200 } "NODE_NAME" } } { "addre.vhd" "" { Text "G:/TASK/DVDT_MORE/addre.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.116 ns) + CELL(0.738 ns) 4.593 ns addre:inst1\|count\[6\] 6 REG LAB_X8_Y14 5 " "Info: 6: + IC(0.116 ns) + CELL(0.738 ns) = 4.593 ns; Loc. = LAB_X8_Y14; Fanout = 5; REG Node = 'addre:inst1\|count\[6\]'" {  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "0.854 ns" { addre:inst1|count~200 addre:inst1|count[6] } "NODE_NAME" } } { "addre.vhd" "" { Text "G:/TASK/DVDT_MORE/addre.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.591 ns ( 56.41 % ) " "Info: Total cell delay = 2.591 ns ( 56.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.002 ns ( 43.59 % ) " "Info: Total interconnect delay = 2.002 ns ( 43.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "4.593 ns" { addre:inst1|count[4] addre:inst1|Add0~294COUT1 addre:inst1|Add0~292COUT1 addre:inst1|Add0~289 addre:inst1|count~200 addre:inst1|count[6] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X0_Y11 X11_Y21 " "Info: The peak interconnect region extends from location X0_Y11 to location X11_Y21" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}