📄 top.sim.rpt
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; Missing 1-Value Coverage ;
+-----------------------------+--------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------------------------+--------------------------------+------------------+
; |top|addre:inst1|Add0~267 ; |top|addre:inst1|Add0~267 ; combout ;
; |top|addre:inst1|Add0~269 ; |top|addre:inst1|Add0~269 ; combout ;
; |top|addre:inst1|Add0~269 ; |top|addre:inst1|Add0~270 ; cout0 ;
; |top|addre:inst1|Add0~269 ; |top|addre:inst1|Add0~270COUT1 ; cout1 ;
; |top|addre:inst1|Add0~271 ; |top|addre:inst1|Add0~271 ; combout ;
; |top|addre:inst1|Add0~271 ; |top|addre:inst1|Add0~272 ; cout0 ;
; |top|addre:inst1|Add0~271 ; |top|addre:inst1|Add0~272COUT1 ; cout1 ;
; |top|addre:inst1|Add0~273 ; |top|addre:inst1|Add0~273 ; combout ;
; |top|addre:inst1|Add0~273 ; |top|addre:inst1|Add0~274 ; cout0 ;
; |top|addre:inst1|Add0~273 ; |top|addre:inst1|Add0~274COUT1 ; cout1 ;
; |top|addre:inst1|Add0~275 ; |top|addre:inst1|Add0~275 ; combout ;
; |top|addre:inst1|Add0~275 ; |top|addre:inst1|Add0~276 ; cout ;
; |top|addre:inst1|Add0~277 ; |top|addre:inst1|Add0~277 ; combout ;
; |top|addre:inst1|Add0~277 ; |top|addre:inst1|Add0~278 ; cout0 ;
; |top|addre:inst1|Add0~277 ; |top|addre:inst1|Add0~278COUT1 ; cout1 ;
; |top|addre:inst1|Add0~279 ; |top|addre:inst1|Add0~279 ; combout ;
; |top|addre:inst1|Add0~279 ; |top|addre:inst1|Add0~280 ; cout0 ;
; |top|addre:inst1|Add0~279 ; |top|addre:inst1|Add0~280COUT1 ; cout1 ;
; |top|addre:inst1|Add0~281 ; |top|addre:inst1|Add0~281 ; combout ;
; |top|addre:inst1|Add0~281 ; |top|addre:inst1|Add0~282 ; cout0 ;
; |top|addre:inst1|Add0~281 ; |top|addre:inst1|Add0~282COUT1 ; cout1 ;
; |top|addre:inst1|Add0~283 ; |top|addre:inst1|Add0~283 ; combout ;
; |top|addre:inst1|Add0~283 ; |top|addre:inst1|Add0~284 ; cout0 ;
; |top|addre:inst1|Add0~283 ; |top|addre:inst1|Add0~284COUT1 ; cout1 ;
; |top|addre:inst1|Add0~285 ; |top|addre:inst1|Add0~285 ; combout ;
; |top|addre:inst1|Add0~285 ; |top|addre:inst1|Add0~286 ; cout ;
; |top|addre:inst1|Add0~287 ; |top|addre:inst1|Add0~287 ; combout ;
; |top|addre:inst1|Add0~287 ; |top|addre:inst1|Add0~288 ; cout0 ;
; |top|addre:inst1|Add0~287 ; |top|addre:inst1|Add0~288COUT1 ; cout1 ;
; |top|addre:inst1|Add0~289 ; |top|addre:inst1|Add0~290 ; cout0 ;
; |top|addre:inst1|Add0~289 ; |top|addre:inst1|Add0~290COUT1 ; cout1 ;
; |top|addre:inst1|Add0~291 ; |top|addre:inst1|Add0~292COUT1 ; cout1 ;
; |top|addre:inst1|Add0~293 ; |top|addre:inst1|Add0~294COUT1 ; cout1 ;
; |top|com:inst|ready ; |top|com:inst|ready ; combout ;
; |top|addre:inst1|count[17] ; |top|addre:inst1|count[17] ; regout ;
; |top|addre:inst1|count[16] ; |top|addre:inst1|count[16] ; regout ;
; |top|addre:inst1|count[15] ; |top|addre:inst1|count[15] ; regout ;
; |top|addre:inst1|count[14] ; |top|addre:inst1|count[14] ; regout ;
; |top|addre:inst1|count[13] ; |top|addre:inst1|count[13] ; regout ;
; |top|addre:inst1|count[12] ; |top|addre:inst1|count[12] ; regout ;
; |top|addre:inst1|count[11] ; |top|addre:inst1|count[11] ; regout ;
; |top|addre:inst1|count[10] ; |top|addre:inst1|count[10] ; regout ;
; |top|addre:inst1|count[9] ; |top|addre:inst1|count[9] ; regout ;
; |top|addre:inst1|count[8] ; |top|addre:inst1|count[8] ; regout ;
; |top|addre:inst1|count[7] ; |top|addre:inst1|count[7] ; regout ;
; |top|addre:inst1|count[6] ; |top|addre:inst1|count[6] ; regout ;
; |top|addre:inst1|Equal0~169 ; |top|addre:inst1|Equal0~169 ; combout ;
; |top|addre:inst1|Equal0~170 ; |top|addre:inst1|Equal0~170 ; combout ;
; |top|addre:inst1|Equal0~171 ; |top|addre:inst1|Equal0~171 ; combout ;
; |top|~GND ; |top|~GND ; combout ;
; |top|dataout[7] ; |top|dataout[7] ; padio ;
; |top|dataout[6] ; |top|dataout[6] ; padio ;
; |top|dataout[5] ; |top|dataout[5] ; padio ;
; |top|dataout[4] ; |top|dataout[4] ; padio ;
; |top|dataout[3] ; |top|dataout[3] ; padio ;
; |top|dataout[2] ; |top|dataout[2] ; padio ;
; |top|dataout[1] ; |top|dataout[1] ; padio ;
; |top|dataout[0] ; |top|dataout[0] ; padio ;
; |top|ready ; |top|ready ; padio ;
; |top|addre[17] ; |top|addre[17] ; padio ;
; |top|addre[16] ; |top|addre[16] ; padio ;
; |top|addre[15] ; |top|addre[15] ; padio ;
; |top|addre[14] ; |top|addre[14] ; padio ;
; |top|addre[13] ; |top|addre[13] ; padio ;
; |top|addre[12] ; |top|addre[12] ; padio ;
; |top|addre[11] ; |top|addre[11] ; padio ;
; |top|addre[10] ; |top|addre[10] ; padio ;
; |top|addre[9] ; |top|addre[9] ; padio ;
; |top|addre[8] ; |top|addre[8] ; padio ;
; |top|addre[7] ; |top|addre[7] ; padio ;
; |top|addre[6] ; |top|addre[6] ; padio ;
; |top|rst ; |top|rst ; combout ;
; |top|change ; |top|change ; combout ;
+-----------------------------+--------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+--------------------------------+--------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------------------+--------------------------------+------------------+
; |top|addre:inst1|Add0~267 ; |top|addre:inst1|Add0~267 ; combout ;
; |top|addre:inst1|Add0~269 ; |top|addre:inst1|Add0~269 ; combout ;
; |top|addre:inst1|Add0~269 ; |top|addre:inst1|Add0~270 ; cout0 ;
; |top|addre:inst1|Add0~269 ; |top|addre:inst1|Add0~270COUT1 ; cout1 ;
; |top|addre:inst1|Add0~271 ; |top|addre:inst1|Add0~271 ; combout ;
; |top|addre:inst1|Add0~271 ; |top|addre:inst1|Add0~272 ; cout0 ;
; |top|addre:inst1|Add0~271 ; |top|addre:inst1|Add0~272COUT1 ; cout1 ;
; |top|addre:inst1|Add0~273 ; |top|addre:inst1|Add0~273 ; combout ;
; |top|addre:inst1|Add0~273 ; |top|addre:inst1|Add0~274 ; cout0 ;
; |top|addre:inst1|Add0~273 ; |top|addre:inst1|Add0~274COUT1 ; cout1 ;
; |top|addre:inst1|Add0~275 ; |top|addre:inst1|Add0~275 ; combout ;
; |top|addre:inst1|Add0~275 ; |top|addre:inst1|Add0~276 ; cout ;
; |top|addre:inst1|Add0~277 ; |top|addre:inst1|Add0~277 ; combout ;
; |top|addre:inst1|Add0~277 ; |top|addre:inst1|Add0~278 ; cout0 ;
; |top|addre:inst1|Add0~277 ; |top|addre:inst1|Add0~278COUT1 ; cout1 ;
; |top|addre:inst1|Add0~279 ; |top|addre:inst1|Add0~279 ; combout ;
; |top|addre:inst1|Add0~279 ; |top|addre:inst1|Add0~280 ; cout0 ;
; |top|addre:inst1|Add0~279 ; |top|addre:inst1|Add0~280COUT1 ; cout1 ;
; |top|addre:inst1|Add0~281 ; |top|addre:inst1|Add0~281 ; combout ;
; |top|addre:inst1|Add0~281 ; |top|addre:inst1|Add0~282 ; cout0 ;
; |top|addre:inst1|Add0~281 ; |top|addre:inst1|Add0~282COUT1 ; cout1 ;
; |top|addre:inst1|Add0~283 ; |top|addre:inst1|Add0~283 ; combout ;
; |top|addre:inst1|Add0~283 ; |top|addre:inst1|Add0~284 ; cout0 ;
; |top|addre:inst1|Add0~283 ; |top|addre:inst1|Add0~284COUT1 ; cout1 ;
; |top|addre:inst1|Add0~285 ; |top|addre:inst1|Add0~285 ; combout ;
; |top|addre:inst1|Add0~285 ; |top|addre:inst1|Add0~286 ; cout ;
; |top|addre:inst1|Add0~287 ; |top|addre:inst1|Add0~287 ; combout ;
; |top|addre:inst1|Add0~287 ; |top|addre:inst1|Add0~288 ; cout0 ;
; |top|addre:inst1|Add0~287 ; |top|addre:inst1|Add0~288COUT1 ; cout1 ;
; |top|addre:inst1|Add0~289 ; |top|addre:inst1|Add0~290 ; cout0 ;
; |top|addre:inst1|Add0~289 ; |top|addre:inst1|Add0~290COUT1 ; cout1 ;
; |top|addre:inst1|Add0~291 ; |top|addre:inst1|Add0~292COUT1 ; cout1 ;
; |top|addre:inst1|Add0~293 ; |top|addre:inst1|Add0~294COUT1 ; cout1 ;
; |top|com:inst|current_state.s0 ; |top|com:inst|current_state.s0 ; regout ;
; |top|addre:inst1|count[17] ; |top|addre:inst1|count[17] ; regout ;
; |top|addre:inst1|count[16] ; |top|addre:inst1|count[16] ; regout ;
; |top|addre:inst1|count[15] ; |top|addre:inst1|count[15] ; regout ;
; |top|addre:inst1|count[14] ; |top|addre:inst1|count[14] ; regout ;
; |top|addre:inst1|count[13] ; |top|addre:inst1|count[13] ; regout ;
; |top|addre:inst1|count[12] ; |top|addre:inst1|count[12] ; regout ;
; |top|addre:inst1|count[11] ; |top|addre:inst1|count[11] ; regout ;
; |top|addre:inst1|count[10] ; |top|addre:inst1|count[10] ; regout ;
; |top|addre:inst1|count[9] ; |top|addre:inst1|count[9] ; regout ;
; |top|addre:inst1|count[8] ; |top|addre:inst1|count[8] ; regout ;
; |top|addre:inst1|count[7] ; |top|addre:inst1|count[7] ; regout ;
; |top|addre:inst1|count[6] ; |top|addre:inst1|count[6] ; regout ;
; |top|addre:inst1|Equal0~169 ; |top|addre:inst1|Equal0~169 ; combout ;
; |top|addre:inst1|Equal0~170 ; |top|addre:inst1|Equal0~170 ; combout ;
; |top|addre:inst1|Equal0~171 ; |top|addre:inst1|Equal0~171 ; combout ;
; |top|~GND ; |top|~GND ; combout ;
; |top|dataout[7] ; |top|dataout[7] ; padio ;
; |top|dataout[6] ; |top|dataout[6] ; padio ;
; |top|dataout[5] ; |top|dataout[5] ; padio ;
; |top|dataout[4] ; |top|dataout[4] ; padio ;
; |top|dataout[3] ; |top|dataout[3] ; padio ;
; |top|dataout[2] ; |top|dataout[2] ; padio ;
; |top|dataout[1] ; |top|dataout[1] ; padio ;
; |top|dataout[0] ; |top|dataout[0] ; padio ;
; |top|addre[17] ; |top|addre[17] ; padio ;
; |top|addre[16] ; |top|addre[16] ; padio ;
; |top|addre[15] ; |top|addre[15] ; padio ;
; |top|addre[14] ; |top|addre[14] ; padio ;
; |top|addre[13] ; |top|addre[13] ; padio ;
; |top|addre[12] ; |top|addre[12] ; padio ;
; |top|addre[11] ; |top|addre[11] ; padio ;
; |top|addre[10] ; |top|addre[10] ; padio ;
; |top|addre[9] ; |top|addre[9] ; padio ;
; |top|addre[8] ; |top|addre[8] ; padio ;
; |top|addre[7] ; |top|addre[7] ; padio ;
; |top|addre[6] ; |top|addre[6] ; padio ;
; |top|st[1] ; |top|st[1] ; padio ;
+--------------------------------+--------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
Info: Processing started: Wed Mar 18 22:17:46 2009
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off top -c top
Info: Using vector source file "G:/TASK/DVDT_MORE/top.vwf"
Info: Inverted registers were found during simulation
Info: Register: |top|addre:inst1|full_temp
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 49.32 %
Info: Number of transitions in simulation is 43242
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Allocated 88 megabytes of memory during processing
Info: Processing ended: Wed Mar 18 22:17:48 2009
Info: Elapsed time: 00:00:02
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