clk_select.vhd

来自「基于FPGA有限状态机的数据采集系统」· VHDL 代码 · 共 17 行

library ieee;
use ieee.std_logic_1164.all;

entity clk_select is
port(clk_sys	:in std_logic;
	clk_cpu		:in std_logic;
	clk_s		:in std_logic;
	clk			:out std_logic);
end clk_select;

architecture behave of clk_select is
	begin
		
		clk<=clk_sys when clk_s='0' else
			clk_cpu	 when clk_s='1' else
			'1';
end behave;