📄 top.map.rpt
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; ; ;
; Total registers ; 28 ;
; Total logic cells in carry chains ; 18 ;
; I/O pins ; 16 ;
; Maximum fan-out node ; clk_select:inst2|clk~16 ;
; Maximum fan-out ; 24 ;
; Total fan-out ; 291 ;
; Average fan-out ; 2.08 ;
+---------------------------------------------+-------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------+
; |top ; 70 (1) ; 28 ; 0 ; 16 ; 0 ; 42 (1) ; 18 (0) ; 10 (0) ; 18 (0) ; 0 (0) ; |top ;
; |addre:inst1| ; 44 (44) ; 19 ; 0 ; 0 ; 0 ; 25 (25) ; 18 (18) ; 1 (1) ; 18 (18) ; 0 (0) ; |top|addre:inst1 ;
; |clk_div:inst3| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; 0 (0) ; |top|clk_div:inst3 ;
; |clk_select:inst2| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|clk_select:inst2 ;
; |com:inst| ; 19 (19) ; 4 ; 0 ; 0 ; 0 ; 15 (15) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |top|com:inst ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
Encoding Type: One-Hot
+----------------------------------------------------------------------------------------------+
; State Machine - |top|com:inst|current_state ;
+------------------+------------------+------------------+------------------+------------------+
; Name ; current_state.s3 ; current_state.s2 ; current_state.s1 ; current_state.s0 ;
+------------------+------------------+------------------+------------------+------------------+
; current_state.s0 ; 0 ; 0 ; 0 ; 0 ;
; current_state.s1 ; 0 ; 0 ; 1 ; 1 ;
; current_state.s2 ; 0 ; 1 ; 0 ; 1 ;
; current_state.s3 ; 1 ; 0 ; 0 ; 1 ;
+------------------+------------------+------------------+------------------+------------------+
+---------------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+----------------------------------------------------+---------------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------------+------------------------+
; com:inst|dataram[7]$latch ; com:inst|current_state.s3 ; yes ;
; com:inst|comb_181 ; com:inst|current_state.s3 ; yes ;
; com:inst|dataram[6]$latch ; com:inst|current_state.s3 ; yes ;
; com:inst|dataram[5]$latch ; com:inst|current_state.s3 ; yes ;
; com:inst|dataram[4]$latch ; com:inst|current_state.s3 ; yes ;
; com:inst|dataram[3]$latch ; com:inst|current_state.s3 ; yes ;
; com:inst|dataram[2]$latch ; com:inst|current_state.s3 ; yes ;
; com:inst|dataram[1]$latch ; com:inst|current_state.s3 ; yes ;
; com:inst|dataram[0]$latch ; com:inst|current_state.s3 ; yes ;
; Number of user-specified and inferred latches = 9 ; ; ;
+----------------------------------------------------+---------------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 28 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 5 ;
; Number of registers using Asynchronous Load ; 18 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; addre:inst1|full_temp ; 4 ;
; Total number of inverted registers = 1 ; ;
+----------------------------------------+---------+
+------------------------------------------------------------+
; Parameter Settings for User Entity Instance: clk_div:inst3 ;
+----------------+-------+-----------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-----------------------------------+
; n ; 9 ; Untyped ;
+----------------+-------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
Info: Processing started: Wed Mar 18 22:17:15 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top
Info: Found 2 design units, including 1 entities, in source file com.vhd
Info: Found design unit 1: com-behave
Info: Found entity 1: com
Info: Found 2 design units, including 1 entities, in source file addre.vhd
Info: Found design unit 1: addre-behave
Info: Found entity 1: addre
Info: Found 1 design units, including 1 entities, in source file top.bdf
Info: Found entity 1: top
Info: Found 2 design units, including 1 entities, in source file clk_select.vhd
Info: Found design unit 1: clk_select-behave
Info: Found entity 1: clk_select
Info: Elaborating entity "top" for the top level hierarchy
Info: Elaborating entity "addre" for hierarchy "addre:inst1"
Info: Elaborating entity "clk_select" for hierarchy "clk_select:inst2"
Warning: Using design file clk_div.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: clk_div-behave
Info: Found entity 1: clk_div
Info: Elaborating entity "clk_div" for hierarchy "clk_div:inst3"
Info: Elaborating entity "com" for hierarchy "com:inst"
Warning (10492): VHDL Process Statement warning at com.vhd(87): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at com.vhd(88): signal "datain" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at com.vhd(95): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at com.vhd(96): signal "dataram" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at com.vhd(79): inferring latch(es) for signal or variable "dataram", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at com.vhd(79): inferred latch for "dataram[0]"
Info (10041): Verilog HDL or VHDL info at com.vhd(79): inferred latch for "dataram[1]"
Info (10041): Verilog HDL or VHDL info at com.vhd(79): inferred latch for "dataram[2]"
Info (10041): Verilog HDL or VHDL info at com.vhd(79): inferred latch for "dataram[3]"
Info (10041): Verilog HDL or VHDL info at com.vhd(79): inferred latch for "dataram[4]"
Info (10041): Verilog HDL or VHDL info at com.vhd(79): inferred latch for "dataram[5]"
Info (10041): Verilog HDL or VHDL info at com.vhd(79): inferred latch for "dataram[6]"
Info (10041): Verilog HDL or VHDL info at com.vhd(79): inferred latch for "dataram[7]"
Info: State machine "|top|com:inst|current_state" contains 4 states
Info: Selected Auto state machine encoding method for state machine "|top|com:inst|current_state"
Info: Encoding result for state machine "|top|com:inst|current_state"
Info: Completed encoding using 4 state bits
Info: Encoded state bit "com:inst|current_state.s3"
Info: Encoded state bit "com:inst|current_state.s2"
Info: Encoded state bit "com:inst|current_state.s1"
Info: Encoded state bit "com:inst|current_state.s0"
Info: State "|top|com:inst|current_state.s0" uses code string "0000"
Info: State "|top|com:inst|current_state.s1" uses code string "0011"
Info: State "|top|com:inst|current_state.s2" uses code string "0101"
Info: State "|top|com:inst|current_state.s3" uses code string "1001"
Info: Registers with preset signals will power-up high
Info: Implemented 140 device resources after synthesis - the final resource count might be different
Info: Implemented 12 input pins
Info: Implemented 42 output pins
Info: Implemented 16 bidirectional pins
Info: Implemented 70 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
Info: Allocated 139 megabytes of memory during processing
Info: Processing ended: Wed Mar 18 22:17:17 2009
Info: Elapsed time: 00:00:02
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