📄 copy of capacitance.asm
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movwf VRCON
; Configure SR Latch
banksel SRCON
; /---------------- 7 - SR1: SR latch enabled. C2OUT I/O pin is latch inverting output
; |/--------------- 6 - SR0:
; ||/-------------- 5 - C1SEN: C1 output has no effect on latch
; |||/------------- 4 - C2REN: C2 output has no effect on latch
; ||||/------------ 3 - PULSS: no pulse
; |||||/----------- 2 - PULSR: pulse Reset input (Reset the latch)
; ||||||/---------- 1 - Unimplemented
; |||||||/--------- 0 - Unimplemented
; ||||||||
; 76543210
movlw b'10000100'
movwf SRCON
; initialize ramp down
banksel PORTC
bsf Vint ; Vint digital output (Vdd)
; make sure Vsen is less than 0.25 * Vdd
banksel CM1CON0 ; compare CVref ( 0.25 * Vdd ) to Vsen
btfsc CM1CON0, C1OUT ; is CVref > Vsen?
goto $ - 1 ; no, wait until CVref > Vsen
banksel COUNT
clrf COUNT ; wait 0.5 us * 3 * 256 = 384 us
decfsz COUNT, F
goto $ - 1
; Step 2 - begin ramp up, start K1 count at 0.25 * Vdd and
; stop count at 0.71825 * Vdd.
banksel TMR1H
clrf TMR1H ; clear Timer1
clrf TMR1L
bsf T1CON, TMR1ON ; enable Timer1 (should not be counting because
; SR latch reset Q_NOT = C2OUT = T1G_NOT = 1)
; Configure SR Latch
banksel SRCON
; /-------------- 5 - C1SEN: C1 output sets SR latch
; |/------------- 4 - C2REN: C2 output has no effect on latch
; ||
; || /----------- 2 - PULSR: pulse Reset input (Reset the latch)
; || |
; 76543210
movlw b'10100100'
movwf SRCON
banksel PORTC
bcf Vint ; Vint digital output (Ground)
; At this point Vsen is ramping up.
; When Vsen crosses C1Vref ( 0.25 * Vdd ) then CVref < Vsen and
; C1OUT_NOT = 1 and sets the SR latch.
; SR latch Q_NOT = C2OUT = T1G_NOT = 0 and enables Timer1 to count.
; detect when Vsen crosses C1Vref ( 0.25 * Vdd ) then reconfigure
; the voltage reference to 0.71825 * Vdd
banksel CM1CON0 ; compare CVref ( 0.25 * Vdd ) to Vsen
btfss CM1CON0, C1OUT ; is CVref < Vsen?
goto $ - 1 ; no, wait until CVref < Vsen
; change CVref to 0.71825 * Vdd
; ( settling time = 10 us max )
; /---------------- 7 - C1VREN: CVref on and routed to C1Vref
; |/--------------- 6 - C2VREN: CVref on and routed to C2Vref
; ||/-------------- 5 - VRR: High range
; |||/------------- 4 - VP6EN: disabled
; ||||/------------ 3 - VR3: 0.71825 * Vdd
; |||||/----------- 2 - VR2:
; ||||||/---------- 1 - VR1:
; |||||||/--------- 0 - VR0:
; ||||||||
; 76543210
movlw b'11001111'
movwf VRCON
; reconfigure SR Latch to reset when Vsen crosses the CVref voltage
banksel SRCON
; /-------------- 5 - C1SEN: C1 output has no effect on latch
; |/------------- 4 - C2REN: C2 output resets SR latch
; ||
; 76543210
movlw b'10010000'
movwf SRCON
; When CVref ( 0.71825 * Vdd ) < Vsen then C2OUT_NOT = 1 and
; resets the SR latch.
; SR latch Q_NOT = C2OUT = T1G_NOT = 1 and disables Timer1.
; detect when CVref < Vsen and record the Timer1 value
banksel CM1CON0 ; compare CVref ( 0.71825 * Vdd ) to Vsen
btfss CM1CON0, C1OUT ; is CVref < Vsen?
goto $ - 1 ; no, wait until CVref < Vsen
banksel T1CON
bcf T1CON, TMR1ON ; disable Timer1
movfw TMR1H ; save K1 count
movwf K1_H
movfw TMR1L
movwf K1_L
banksel COUNT
clrf COUNT ; wait 0.5 us * 3 * 256 = 384 us
decfsz COUNT, F
goto $ - 1
; Step 3 - begin ramp down, start k2 count at 0.71825 * Vdd and
; stop count at 0.25 * Vdd
banksel TMR1H
clrf TMR1H ; clear Timer1
clrf TMR1L
bsf T1CON, TMR1ON ; enable Timer1 (should not be counting because
; SR latch reset: Q_NOT = C2OUT = T1G_NOT = 1)
; Configure Comparator C1
; ( settling time = 10 us max )
banksel CM1CON0
bcf CM1CON0, C1POL ; C1OUT logic is not inverted
; Configure Comparator C2
; ( settling time = 10 us max )
bcf CM2CON0, C2POL ; C2OUT logic is not inverted
; Configure SR Latch
banksel SRCON
; /-------------- 5 - C1SEN: C1 output sets SR latch
; |/------------- 4 - C2REN: C2 output has no effect on latch
; ||
; || /----------- 2 - PULSR: pulse Reset input (Reset the latch)
; || |
; 76543210
movlw b'10100100'
movwf SRCON
banksel PORTC
bsf Vint ; Vint digital output (Vdd)
; At this point Vsen is ramping down.
; When Vsen crosses C1Vef ( 0.71825 * Vdd ) then CVref > Vsen and
; C1OUT = 1 and sets the SR latch.
; SR latch Q_NOT = C2OUT = T1G_NOT = 0 and enables Timer1 to count
; detect when Vsen crosses C1Vref ( 0.71825 * Vdd ) then reconfigure
; the voltage reference to 0.25 * Vdd
banksel CM1CON0 ; compare CVref ( 0.25 * Vdd ) to Vsen
btfss CM1CON0, C1OUT ; is CVref > Vsen?
goto $ - 1 ; no, wait until CVref > Vsen
; change CVref to 0.25 * Vdd
; ( settling time = 10 us max )
; /---------------- 7 - C1VREN: CVref on and routed to C1Vref
; |/--------------- 6 - C2VREN: CVref on and routed to C2Vref
; ||/-------------- 5 - VRR: Low range
; |||/------------- 4 - VP6EN: disabled
; ||||/------------ 3 - VR3: 0.25 * Vdd
; |||||/----------- 2 - VR2:
; ||||||/---------- 1 - VR1:
; |||||||/--------- 0 - VR0:
; ||||||||
; 76543210
movlw b'11100110'
movwf VRCON
; reconfigure SR Latch to reset when Vsen crosses the CVref voltage
banksel SRCON
; /-------------- 5 - C1SEN: C1 output has no effect on latch
; |/------------- 4 - C2REN: C2 output resets SR latch
; ||
; 76543210
movlw b'10010000'
movwf SRCON
; When CVref ( 0.25 * Vdd ) > Vsen then C2OUT = 1 and
; resets the SR latch.
; SR latch Q_NOT = C2OUT = T1G_NOT = 1 and disables Timer1.
; detect when CVref > Vsen and record the Timer1 value
banksel CM1CON0 ; compare CVref ( 0.25 * Vdd ) to Vsen
btfss CM1CON0, C1OUT ; is CVref > Vsen?
goto $ - 1 ; no, wait until CVref > Vsen
banksel T1CON
bcf T1CON, TMR1ON ; disable Timer1
movfw TMR1H ; save K2 count
movwf K2_H
movfw TMR1L
movwf K2_L
banksel COUNT
clrf COUNT ; wait 0.5 us * 3 * 256 = 384 us
decfsz COUNT, F
goto $ - 1
; Step 4 - Calculate capacitance
movfw K1_L ; add K1 and K2, answer in K2
addwf K2_L, F
btfsc STATUS, C
incf K2_H, F
movfw K1_H
addwf K2_H, F
bcf STATUS, C ; divide answer by 2 (result is average)
rrf K2_H, F
rrf K2_L, F
; Step 5 - Wait
; banksel COUNT
; clrf COUNT ; wait 0.5 us * 3 * 256 = 384 us
; decfsz COUNT, F
; goto $ - 1
return
;----------------------------------------------------------------------
end ; end of program directive
;----------------------------------------------------------------------
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