copy of capacitance.asm

Synchronous Serial Communications (SSC) is a synchronous serial communications protocol between

;----------------------------------------------------------------------
; 
; Copyright 2005 Microchip Technology Inc.
; 
; Microchip Technology Inc. ("Microchip") licenses this software to
; you solely for use with Microchip products. The software is owned
; by Microchip and is protected under applicable copyright laws. All
; rights reserved.
; 
; SOFTWARE IS PROVIDED IN AN "AS IS." MICROCHIP EXPRESSLY DISCLAIMS ANY
; WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
; PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL MICROCHIP
; BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
; DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
; PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
; BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
; ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
; 
;----------------------------------------------------------------------
;
;   Filename:           capacitance.asm
;   Microcontroller:    PIC16F690
;   Assembled using:    MPLAB IDE v7.20
;
;   Author:             Steven Bible
;   Company:            Microchip Technology Inc.
;
;----------------------------------------------------------------------
;
;   Program Description:
;
;   
;
;----------------------------------------------------------------------
;
;   Revision History:
;
;   Ver. 0.1 - 2005-08-29: Initial write
;   Ver. 0.2 - 2005-11-22: Modified for relocateable module
;
;----------------------------------------------------------------------

    errorlevel  -302                ; suppress message 302 from list file

;----------------------------------------------------------------------
; Include Files
;----------------------------------------------------------------------

#include    "main.inc"              ; Project defines

;----------------------------------------------------------------------
; Local Defines
;----------------------------------------------------------------------

; none

;----------------------------------------------------------------------
; Variables
;----------------------------------------------------------------------

;--------------------
; Uninitialized Data Section
;
; The RES directive reserves space for data storage.

        udata

COUNT           res 1               ; General Purpose counter variable

    ; count variables

K1_H            res 1               ; 16-bit K1 count
K1_L            res 1
K2_H            res 1               ; (Global) 16-bit K2 count
K2_L            res 1


;--------------------
; Shared Uninitialized Data Section
;
; Variables that are allocated in RAM that ais shared across all RAM banks (unbanked RAM). 
; The RES directive reserves space for data storage.

;        udata_shr

; none

;--------------------
; Global Variables
;
; Variables defined in this module that are made available to other 
; modules. The <label> must be defined prior to using the GLOBAL
; directive in this module. 

    global  K2_H
    global  K2_L


;----------------------------------------------------------------------
; Begin Executable Code Segment
;----------------------------------------------------------------------

;[<label>]  code    [<ROM_Address>]

        code

;----------------------------------------------------------------------
; Subroutine: Initialize Capacitive 
;   
; Description: 
;   
; Constants: 
;   
; Global Variables: 
;   
; Initialization: 
;   
; Output: 
;   
;----------------------------------------------------------------------

CAP_Init
    global  CAP_Init

;----------------------------------------
; TIMER1 Module with Gate Control (Section 6)
;
; The TIMER1 Control Register (T1CON) is used to enable/disable TIMER1
; and select various features of the TIMER1 module.

        banksel T1CON               ; Bank 0

        bcf     T1CON, TMR1CS       ; TIMER1 Clock Source Select: Internal Clock (Fosc/4)

        ; If TMR1CS=0 this bit is ignored
        bsf     T1CON, NOT_T1SYNC   ; TIMER1 External Clock Input Sync Control: do not syncronize external clock input

        ; T1OSCEN only if INTOSC without CLKOUT oscillator is active, else ignored
        bcf     T1CON, T1OSCEN      ; LP Oscillator Enable Control: LP oscillator off

        ; TIMER1 Input Prescale Select: 1:1
        bcf     T1CON, T1CKPS1      ; TIMER1 Input Clock Prescale Select bit 1
        bcf     T1CON, T1CKPS0      ; TIMER1 Input Clock Prescale Select bit 0

        ; TMR1GE only if TMR1ON = 1, else ignored
        bsf     T1CON, TMR1GE       ; TIMER1 Gate Enable: Timer1 is on when T1G_NOT = 0

        bcf     T1CON, T1GINV       ; TIMER1 gate is not inverted

        bcf     T1CON, TMR1ON       ; TIMER1: disabled


        return


;----------------------------------------------------------------------
; Subroutine: Read Capacitance
;   
; Description: Read capacitance using a dual slope integration technique.
;              Capacitance is reported as counts from Timer1.
;   
; Constants: 
;   
; Global Variables: K2_H, K2_L
;   
; Initialization: call CAP_Init prior to calling this routine.
;   
; Output: K2_H:K2_L is a global variable contains 16-bit capacitance
;         value.
;   
;----------------------------------------------------------------------

CAP_Read
    global  CAP_Read

    ; Step 1 - Initialize

        ; Configure Comparator C1
        ; ( settling time = 10 us max )
        banksel CM1CON0
        ;         /---------------- 7 - C1ON: C1 Comparator is enable
        ;         |/--------------- 6 - C1OUT
        ;         ||/-------------- 5 - C1OE: C1OUT is internal only
        ;         |||/------------- 4 - C1POL: C1OUT logic is inverted
        ;         ||||/------------ 3 - Unimplemented
        ;         |||||/----------- 2 - C1R: C1VP connects to C1Vref output
        ;         ||||||/---------- 1 - C1CH1: C1VN connects to RC1/C12IN-
        ;         |||||||/--------- 0 - C1CH0:
        ;         ||||||||
        ;         76543210
        movlw   b'10010101'
        movwf   CM1CON0

        ; Configure Comparator C2
        ; ( settling time = 10 us max )
        ;         /---------------- 7 - C2ON: C2 Comparator is enable
        ;         |/--------------- 6 - C2OUT
        ;         ||/-------------- 5 - C2OE: C2OUT is present on RC4/C2OUT
        ;         |||/------------- 4 - C2POL: C2OUT logic is inverted
        ;         ||||/------------ 3 - Unimplemented
        ;         |||||/----------- 2 - C2R: C2VP connects to C2Vref output
        ;         ||||||/---------- 1 - C2CH1: C2VN connects to RC1/C12IN-
        ;         |||||||/--------- 0 - C2CH0:
        ;         ||||||||
        ;         76543210
        movlw   b'10110101'
        movwf   CM2CON0

        ;         /---------------- 7 - MC1OUT
        ;         |/--------------- 6 - MC2OUT
        ;         ||/-------------- 5 - Unimplemented
        ;         |||/------------- 4 - Unimplemented
        ;         ||||/------------ 3 - Unimplemented
        ;         |||||/----------- 2 - Unimplemented
        ;         ||||||/---------- 1 - T1GSS: Timer1 gate source is RA4/T1G_NOT
        ;         |||||||/--------- 0 - C2SYNC: C2 output is asynchronous
        ;         ||||||||
        ;         76543210
        movlw   b'00000010'
        movwf   CM2CON1

        ; Configure Comparator Reference
        ; ( settling time = 10 us max )
        ;         /---------------- 7 - C1VREN: CVref on and routed to C1Vref
        ;         |/--------------- 6 - C2VREN: CVref on and routed to C2Vref
        ;         ||/-------------- 5 - VRR: Low range
        ;         |||/------------- 4 - VP6EN: disabled
        ;         ||||/------------ 3 - VR3: 0.25 * Vdd
        ;         |||||/----------- 2 - VR2:
        ;         ||||||/---------- 1 - VR1:
        ;         |||||||/--------- 0 - VR0:
        ;         ||||||||
        ;         76543210
        movlw   b'11100110'