initialize_f690.asm

Synchronous Serial Communications (SSC) is a synchronous serial communications protocol between

;
; Four of the PORTB pins are individually configurable as an interrupt-
; on-change pin. Control bits IOCB<7:4> enable or disable the interrupt 
; function for each pin. Refer to Register 4-8. The interrupt-on-change
; is disabled on a Power-on Reset.
;
; Note: Global, port change, and peripheral interrupt enables 
;       (GIE, RAIE and PEIE) must be enabled for individual interrupts
;       to be recognized (see INTCON register below).

        banksel IOCB                ; Bank 2

;    PORTB Pins = 7654xxxx
        movlw   B'00000010'         ; PORTB interrupt-on-change disabled
        movwf   IOCB

;----------------------------------------
; OPTION Register (OPTION_REG) (Section 2.2.2.2)
;
; The OPTION_REG contains control bits to configure:
;   Weak pull-ups on PORTA (see also WPUA Register above)
;   External RA2/INT interrupt
;   TMR0
;   TMR0/WDT prescaler

        banksel OPTION_REG          ; Bank 1

        bsf     OPTION_REG, NOT_RABPU ; PORTA/PORTB pull-ups: disabled

        bsf     OPTION_REG, INTEDG  ; Interrupt Edge: on rising edge of RA2/INT pin

; TIMER0 Module (Section 5.0)
;
; The Timer0 module timer/counter has the following features:
;   8-bit timer/counter
;   Readable and writable
;   8-bit software programmable prescaler
;   Internal or external clock select
;   Interrupt on overflow from 0xFF to 0x00
;   Edge select for external clock

        bcf     OPTION_REG, T0CS    ; TMR0 Clock Source: internal instruction cycle (CLKOUT)
        bcf     OPTION_REG, T0SE    ; TMR0 Source Edge: increment low-to-high transition on GP2/T0CKI pin

        bcf     OPTION_REG, PSA     ; Prescaler Assignment: assigned to TIMER0

        ; TMR0 Prescaler Rate: 1:2
        bcf     OPTION_REG, PS2     ; Prescaler Rate Select bit 2
        bcf     OPTION_REG, PS1     ; Prescaler Rate Select bit 1
        bcf     OPTION_REG, PS0     ; Prescaler Rate Select bit 0

;----------------------------------------
; TIMER1 Module with Gate Control (Section 6)
;
; The TIMER1 Control Register (T1CON) is used to enable/disable TIMER1
; and select various features of the TIMER1 module.

        banksel T1CON               ; Bank 0

        bcf     T1CON, TMR1CS       ; TIMER1 Clock Source Select: Internal Clock (Fosc/4)

        ; If TMR1CS=0 this bit is ignored
        bsf     T1CON, NOT_T1SYNC   ; TIMER1 External Clock Input Sync Control: do not syncronize external clock input

        ; T1OSCEN only if INTOSC without CLKOUT oscillator is active, else ignored
        bcf     T1CON, T1OSCEN      ; LP Oscillator Enable Control: LP oscillator off

        ; TIMER1 Input Prescale Select: 1:1
        bcf     T1CON, T1CKPS1      ; TIMER1 Input Clock Prescale Select bit 1
        bcf     T1CON, T1CKPS0      ; TIMER1 Input Clock Prescale Select bit 0

        ; TMR1GE only if TMR1ON = 1, else ignored
        bcf     T1CON, TMR1GE       ; TIMER1 Gate Enable: Timer1 is on

        bcf     T1CON, T1GINV       ; TIMER1 gate is not inverted

        bcf     T1CON, TMR1ON       ; TIMER1: disabled

;----------------------------------------
; TIMER2 Module (Section 7)
;
; The Timer2 module timer has the following features:
;   - 8-bit timer (TMR2 register)
;   - 8-bit period register (PR2)
;   - Readable and writable (both registers)
;   - Software programmable prescaler (1:1, 1:4, 1:16)
;   - Software programmable postscaler (1:1 to 1:16)
;   - Interrupt on TMR2 match with PR2

        banksel T2CON               ; Bank 0

        ; Timer2 Output Postscale Select: 1:1 postscale
        bcf     T2CON, TOUTPS3
        bcf     T2CON, TOUTPS2
        bcf     T2CON, TOUTPS1
        bcf     T2CON, TOUTPS0

        ; Timer2 Clock Prescale Select: Prescaler is 1
        bcf     T2CON, T2CKPS1
        bcf     T2CON, T2CKPS0

        bcf     T2CON, TMR2ON       ; Timer2: Off

;----------------------------------------
; Comparator Module (Section 8)
; Voltage Reference Module (Section 9)
;
; The PIC16F690 devices have one analog comparator. The inputs to
; the comparator are multiplexed with the RA0 and RA1 pins. There is
; an on-chip Comparator Voltage Reference that can also be applied to
; an input of the comparator. In addition, RA2 can be configured as
; the comparator output. The Comparator Control Register (CMCON)
; contains bits to control the comparator. The Voltage Reference
; Control Register (VRCON) controls the voltage reference module.

        banksel CM1CON0             ; Bank 2

        bcf     CM1CON0, C1ON       ; C1 Comparator: disabled
        bcf     CM2CON0, C2ON       ; C2 Comparator: disabled

        ; VRCON (Register 9-1)

        bcf     VRCON, C1VREN       ; Comparator 1 Voltage Reference: 0.6V constant
        bcf     VRCON, C2VREN       ; Comparator 2 Voltage Reference: 0.6V constant

        bcf     VRCON, VP6EN        ; 0.6V Reference: disabled

;        bcf     VRCON, VRR          ; CVref Range Selection: High Range

;        bcf     VRCON, VR3          ; CVref value selection bit 3
;        bcf     VRCON, VR2          ; CVref value selection bit 2
;        bcf     VRCON, VR1          ; CVref value selection bit 1
;        bcf     VRCON, VR0          ; CVref value selection bit 0

;----------------------------------------
; Analog-to-Digital Converter (A/D) Module (Section 10.0)
;
; The analog-to-digital converter (A/D) allows conversion of an analog
; input signal to a 10-bit binary representation of that signal. The
; PIC16F690 has twelve analog inputs, plus two internal inputs, 
; multiplexed into one sample and hold circuit. 
;
; There are four registers to control the functions of the A/D module:
;   A/D Control Register 0 (ADCON0)
;   A/D Control Register 1 (ADCON1)
;   Analog Select Register (ANSEL)
;   Analog Select High Register (ANSELH)
;
; Note: When using PORT pins as analog inputs, ensure the TRISA, TRISB
; or TRISC register bits are set (= 1) for input.

        banksel ADCON0              ; Bank 0

        bcf     ADCON0, ADFM        ; A/D Result Formed: left justified
        bcf     ADCON0, VCFG        ; Voltage Reference: Vdd

        bcf     ADCON0, ADON        ; ADC is shut-off and consumes no operating current

        banksel ADCON1              ; Bank 1

        ; select A/D Conversion Clock Source: Fosc/16
        bsf     ADCON1, ADCS2       ; A/D Conversion Clock Select bit 2
        bcf     ADCON1, ADCS1       ; A/D Conversion Clock Select bit 1
        bsf     ADCON1, ADCS0       ; A/D Conversion Clock Select bit 0

        banksel ANSELH              ; Bank 2

        ; select PORT pins that will be analog inputs: 
        bcf     ANSELH, ANS11       ; Analog Select RB5/AN11: digital I/O
        bcf     ANSELH, ANS10       ; Analog Select RB4/AN10: digital I/O
        bcf     ANSELH, ANS9        ; Analog Select RC7/AN9: digital I/O
        bcf     ANSELH, ANS8        ; Analog Select RC6/AN8: digital I/O

        bcf     ANSEL, ANS7         ; Analog Select RC3/AN7: digital I/O
        bcf     ANSEL, ANS6         ; Analog Select RC2/AN6: digital I/O
        bcf     ANSEL, ANS5         ; Analog Select RC1/AN5: digital I/O
        bcf     ANSEL, ANS4         ; Analog Select RC0/AN4: digital I/O
        bcf     ANSEL, ANS3         ; Analog Select RA3/AN3: digital I/O
        bcf     ANSEL, ANS2         ; Analog Select RA2/AN2: digital I/O
        bcf     ANSEL, ANS1         ; Analog Select RA1/AN1/Vref: digital I/O
        bcf     ANSEL, ANS0         ; Analog Select RA0/AN0: digital I/O

;----------------------------------------
; Enhanced Capture/Compare/PWM+ (ECCP+) Module (Section 12)
;
; The enhanced Capture/Compare/PWM+ (ECCP+) module contains a 16-bit
; register which can operate as a:
;   - 16-bit Capture register
;   - 16-bit Compare register
;   - PWM Master/Slave Duty Cycle register
;
; The CCP1CON register controls the operation of ECCP+.

        banksel CCP1CON             ; Bank 0

        ; ECCP Mode Select: CCP off (resets ECCP module)
        bcf     CCP1CON, CCP1M3
        bcf     CCP1CON, CCP1M2
        bcf     CCP1CON, CCP1M1
        bcf     CCP1CON, CCP1M0

;----------------------------------------
; Enhanced Universal Asynchronous Receiver Transmitter (EUSART) (Section 13)
;
; The USART can be configured in the following modes:
;   - Asynchronous (full-duplex) with:
;       - Auto wake-up on character reception
;       - Auto baud calibration
;       - 12-bit Break character transmission
;   - Synchronous - Master (half-duplex) with selectable clock polarity
;   - Synchronous - Slave (half-duplex) with selectable clock polarity
;
; To configure pins RB5/AN11/RX/DT and RB7/TX/CK to the USART set bits:
;   - SPEN (RCSTA<7>) = 1
;   - TRISB<5> = 1
;   - TRISB<7> = 1
;   NOTE: The USART control will automatically reconfigure the pin from
;         input to output as needed.

        ; hold the USART in reset until configuration is complete

        banksel RCSTA               ; Bank 0

        bcf     RCSTA, SPEN         ; Serial Port Enable bit: serial port disabled

;----------------------------------------
; Synchronous Serial Port Module (Section 13)
;
; The Synchronous Serial Port (SSP) module is a serial interface used to
; communicate with other peripheral or microcontroller devices. These 
; peripheral devices may be serial EEPROMs, shift registers, display
; drivers, A/D converters, etc. The SSP module can operate in one of two
; modes:
;   - Serial Peripheral Interface (SPI)
;   - Inter-Integrated Circuit (I2C)


        banksel SSPSTAT
        clrf    SSPSTAT

        banksel SSPCON
        bcf     SSPCON, SSPEN       ; Synchronous Serial Port Enable: Disabled


;----------------------------------------

        return

;----------------------------------------------------------------------
        end                         ; end of program directive
;----------------------------------------------------------------------