syscon_core.c

sigma yamon yamon-src-02[1].06.tar.gz

             sys_corecard == MIPS_REVISION_CORID_CORE_FPGA2 ||
             sys_corecard == MIPS_REVISION_CORID_CORE_EMUL_SYS )
    {
	int ix;
	ram_range_size = CORE_SYS_PCIMEM_BASE;

        pci_mem_start  = CORE_SYS_PCIMEM_BASE;
	pci_mem_size   = CORE_SYS_PCIIO_BASE - CORE_SYS_PCIMEM_BASE;

	/* On msc01 v1.0, pci_mem_size is limited */
	n = -(REG(MSC01_PCI_REG_BASE,  MSC01_PCI_SC2PMMSKL));
	if (n < pci_mem_size) pci_mem_size = n;

	pci_mem_offset = 0;
	pci_io_start   = 0;
	pci_io_size    = CORE_SYS_PCIIO_SIZE;
	pci_io_offset  = CORE_SYS_PCIIO_BASE;
sead_msc01:
        /* System Controller type */
	n = REG(MSC01_BIU_REG_BASE, MSC01_SC_ID);
	switch ( (n & MSC01_SC_ID_ID_MSK) >> MSC01_SC_ID_ID_SHF )
	{
	  case 1: strcat(name_msc01, " EC-32"); break;
	  case 2: strcat(name_msc01, " EC-64"); break;
	  case 3: strcat(name_msc01, " MGB"); break;
	  case 8: strcat(name_msc01, " OCP"); break;
	}

        /* System Controller Version String */
	n = REG(MSC01_BIU_REG_BASE, MSC01_SC_ID);
	ix = sprintf(version_syscntrl,"%d.%d   ", (n & MSC01_SC_ID_MAR_MSK)
	                                            >> MSC01_SC_ID_MAR_SHF,
	                                          (n & MSC01_SC_ID_MIR_MSK)
	                                            >> MSC01_SC_ID_MIR_SHF);
	n = REG(MSC01_MC_REG_BASE, MSC01_MC_HC_DDR);
	ix += sprintf(&version_syscntrl[ix],
                      (n & MSC01_MC_HC_DDR_DDR_BIT) ? "DDR" : "SDR");
	n = REG(MSC01_MC_REG_BASE, MSC01_MC_HC_FMDW);
	board_systemram_clkrat_msc01_read(&s, NULL, sizeof(s));
	sprintf(&version_syscntrl[ix],
                ((n & MSC01_MC_HC_FMDW_FMDW_BIT) ? "-FW-%s" : "-HW-%s"), s);
    }
    else
    {
	ram_range_size = nb_ram_size;

        pci_mem_start  = nb_pci_mem_start;
	pci_mem_size   = nb_pci_mem_size;
	pci_mem_offset = nb_pci_mem_offset;
	pci_io_start   = nb_pci_io_start;
	pci_io_size    = nb_pci_io_size;
	pci_io_offset  = nb_pci_io_offset;

        /* System Controller Version String */

        pci_config_read32(0,0,0,PCI_CCREV,&n);
        n = (n & PCI_CCREV_REVID_MSK) >> PCI_CCREV_REVID_SHF;
        switch (n)
        {
          case 0x03: strcpy( version_syscntrl, "GT_64120-B-4" );
                     break;
          case 0x10: /* fall through */
          case 0x11: /* fall through */
          case 0x12: strcpy( version_syscntrl, "GT_64120A-B-x" );
                     version_syscntrl[12] = (n & 0xf) | '0';
                     break;
        }
    }

    /**** Register objects ****/

    /* Names of Core cards */

    if (sys_corecard != MIPS_REVISION_CORID_SEAD_MSC01)
    {
        syscon_register_id_core( SYSCON_BOARD_CORECARD_NAME_ID,
	     /* Galileo based */
	     syscon_string_read, 
	         (sys_corecard == MIPS_REVISION_CORID_CORE_LV) ?
		     name_core_lv :
	         (sys_corecard == MIPS_REVISION_CORID_CORE_FPGA ||
		  sys_corecard == MIPS_REVISION_CORID_CORE_FPGAr2) ?
		     name_core_fpga :
		     name_qed_rm5261,
	     NULL,	         NULL,
	     /* SysCtrl based */
	      syscon_string_read,
	         (sys_corecard == MIPS_REVISION_CORID_CORE_SYS) ?
		     name_core_sys :
	         (sys_corecard == MIPS_REVISION_CORID_CORE_FPGA2) ?
		     name_core_fpga2 : name_core_emul,
	     NULL,		 NULL,
	     /* Bonito64 based */
	     syscon_string_read, 
	         (sys_corecard == MIPS_REVISION_CORID_BONITO64) ?
		     name_core_bonito :
	         (sys_corecard == MIPS_REVISION_CORID_CORE_20K) ?
		     name_core_20k : name_core_emul,
	     NULL,		 NULL );
    }

    /* Names/revision of System controller */

    syscon_register_id_core( SYSCON_SYSCTRL_NAME_ID,
	     /* Galileo based */
	     syscon_string_read, (void *)name_galileo,
	     NULL,	         NULL,
	     /* SysCtrl based */
	     syscon_string_read, (void *)name_msc01,
	     NULL,		 NULL,
	     /* Bonito64 based */
	     syscon_string_read, (void *)&name_core_bonito[4],
	     NULL,		 NULL );

    syscon_register_id_core( SYSCON_SYSCTRL_REV_ID,
	     /* Galileo based */
	     syscon_string_read, (void *)version_syscntrl,
	     NULL,	         NULL,
	     /* SysCtrl based */
	     syscon_string_read, (void *)version_syscntrl,
	     NULL,		 NULL,
	     /* Bonito64 based */
	     syscon_string_read, (void *)version_syscntrl,
	     NULL,		 NULL );

    /* SDRAM parameters */

    syscon_register_generic( SYSCON_BOARD_SYSTEMRAM_BASE_ID,
	     syscon_uint32_read, (void *)&ram_range_base,
	     NULL,		 NULL );

    syscon_register_generic( SYSCON_BOARD_SYSTEMRAM_SIZE_ID,
	     syscon_uint32_read, (void *)&ram_range_size,
	     NULL,		 NULL );

    syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_REFRESH_NS_CFG_ID,
	     /* Galileo based */
	     board_systemram_refresh_ns_gt64120_read,   NULL,
	     board_systemram_refresh_ns_gt64120_write,  NULL,
	     /* SysCtrl based */
	     board_systemram_refresh_ns_msc01_read,     NULL,
	     board_systemram_refresh_ns_msc01_write,    NULL,
	     /*  Bonito64 based
	      *  No write, since refresh is configured by setting :
	      *
	      *  1) CPUCLOCKPERIOD field of Bonito64 IODEVCFG register 
	      *  2) DRAMRFSHMULT   field of Bonito64 SDCFG regiter.
	      *  
	      *  This is done by initialisation code.
	      */
	     board_systemram_refresh_ns_bonito64_read,  NULL,
	     NULL,					NULL );

    syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_SRASPRCHG_CYCLES_CFG_ID,
	     /* Galileo based */
	     board_systemram_srasprchg_cycles_gt64120_read,   NULL,
	     board_systemram_srasprchg_cycles_gt64120_write,  NULL,
	     /* SysCtrl based */
	     board_systemram_srasprchg_cycles_msc01_read,     NULL,
	     NULL,				              NULL,
	     /* Bonito64 based */
	     board_systemram_srasprchg_cycles_bonito64_read,  NULL,
	     board_systemram_srasprchg_cycles_bonito64_write, NULL );

    syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_SRAS2SCAS_CYCLES_CFG_ID,
	     /* Galileo based */
	     board_systemram_sras2scas_cycles_gt64120_read,   NULL,
	     board_systemram_sras2scas_cycles_gt64120_write,  NULL,
	     /* SysCtrl based */
	     board_systemram_sras2scas_cycles_msc01_read,     NULL,
	     NULL,				              NULL,
	     /* Bonito64 based */
	     board_systemram_sras2scas_cycles_bonito64_read,  NULL,
	     board_systemram_sras2scas_cycles_bonito64_write, NULL );

    syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_CASLAT_CYCLES_CFG_ID,
	     /* Galileo based */
	     board_systemram_caslat_cycles_gt64120_read,  NULL,
	     NULL,					  NULL,
	     /* SysCtrl based */
	     board_systemram_caslat_cycles_msc01_read,    NULL,
	     NULL,					  NULL,
	     /* Bonito64 based */
	     board_systemram_caslat_cycles_bonito64_read, NULL,
	     NULL,					  NULL );

    syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_READ_BURSTLEN_CFG_ID,
	     /* Galileo based */
	     board_systemram_rw_burstlen_gt64120_read,  NULL,
	     NULL,				        NULL,
	     /* SysCtrl based */
	     board_systemram_rw_burstlen_msc01_read,    NULL,
	     NULL,				        NULL,
	     /* Bonito64 based */
	     board_systemram_rw_burstlen_bonito64_read, NULL,
	     NULL,				        NULL );

    syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_WRITE_BURSTLEN_CFG_ID,
	     /* Galileo based */
	     board_systemram_rw_burstlen_gt64120_read,  NULL,
	     NULL,				        NULL,
	     /* SysCtrl based */
	     board_systemram_rw_burstlen_msc01_read,    NULL,
	     NULL,				        NULL,
	     /* Bonito64 based */
	     board_systemram_rw_burstlen_bonito64_read, NULL,
	     NULL,				        NULL );

    syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_CSLAT_CYCLES_CFG_ID,
	     /* Galileo based */
	     NULL,				        NULL,
	     NULL,					NULL,
	     /* SysCtrl based */
	     board_systemram_cslat_cycles_msc01_read,	NULL,
	     NULL,					NULL,
	     /* Bonito64 based */
	     NULL,				        NULL,
	     NULL,					NULL );

    syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_WRLAT_CYCLES_CFG_ID,
	     /* Galileo based */
	     NULL,				        NULL,
	     NULL,					NULL,
	     /* SysCtrl based */
	     board_systemram_wrlat_cycles_msc01_read,	NULL,
	     NULL,					NULL,
	     /* Bonito64 based */
	     NULL,				        NULL,
	     NULL,					NULL );

    syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_RDDEL_CYCLES_CFG_ID,
	     /* Galileo based */
	     NULL,				        NULL,
	     NULL,					NULL,
	     /* SysCtrl based */
	     board_systemram_rddel_cycles_msc01_read,	NULL,
	     NULL,					NULL,
	     /* Bonito64 based */
	     NULL,				        NULL,
	     NULL,					NULL );

    syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_DDR_CFG_ID,
	     /* Galileo based */
	     NULL,				        NULL,
	     NULL,					NULL,
	     /* SysCtrl based */
	     board_systemram_ddr_msc01_read,		NULL,
	     NULL,					NULL,
	     /* Bonito64 based */
	     NULL,				        NULL,
	     NULL,					NULL );

    syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_FW_CFG_ID,
	     /* Galileo based */
	     NULL,				        NULL,
	     NULL,					NULL,
	     /* SysCtrl based */
	     board_systemram_fw_msc01_read,		NULL,
	     NULL,					NULL,
	     /* Bonito64 based */
	     NULL,				        NULL,
	     NULL,					NULL );

    syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_CLKRAT_CFG_ID,
	     /* Galileo based */
	     NULL,				        NULL,
	     NULL,					NULL,
	     /* SysCtrl based */
	     board_systemram_clkrat_msc01_read,		NULL,
	     NULL,					NULL,
	     /* Bonito64 based */
	     NULL,				        NULL,
	     NULL,					NULL );

    syscon_register_id_core( SYSCON_BOARD_SYSTEMRAM_PARITY_CFG_ID,
	     /* Galileo based */
	     NULL,				        NULL,
	     NULL,					NULL,
	     /* SysCtrl based */
	     board_systemram_parity_msc01_read,		NULL,
	     NULL,					NULL,
	     /* Bonito64 based */
	     NULL,				        NULL,
	     NULL,					NULL );

    syscon_register_id_core( SYSCON_SYSCTRL_WC_CFG_ID,
	     /* Galileo based */
	     NULL,				        NULL,
	     NULL,					NULL,
	     /* SysCtrl based */
	     board_systemram_wc_msc01_read,		NULL,
	     NULL,					NULL,
	     /* Bonito64 based */
	     NULL,				        NULL,
	     NULL,					NULL );

    syscon_register_generic( SYSCON_SYSCTRL_REGADDR_BASE_ID,
	     board_sysctrl_regaddrbase_generic_read,	NULL,
	     NULL,					NULL );

    syscon_register_id_core( SYSCON_SYSCTRL_SYSID_ID,
	     /* Galileo based */
	     NULL,				        NULL,
	     NULL,					NULL,
	     /* SysCtrl based */
	     sysctrl_sysid_msc01_read,			NULL,
	     NULL,					NULL,
	     /* Bonito64 based */
	     NULL,				        NULL,
	     NULL,					NULL );

    syscon_register_id_core( SYSCON_SYSCTRL_PBCREV_MAJOR_ID,
	     /* Galileo based */
	     NULL,				        NULL,
	     NULL,					NULL,
	     /* SysCtrl based */
	     sysctrl_pbcrev_maj_msc01_read,		NULL,
	     NULL,					NULL,
	     /* Bonito64 based */
	     NULL,				        NULL,
	     NULL,					NULL );

    syscon_register_id_core( SYSCON_SYSCTRL_PBCREV_MINOR_ID,
	     /* Galileo based */
	     NULL,				        NULL,
	     NULL,					NULL,
	     /* SysCtrl based */
	     sysctrl_pbcrev_min_msc01_read,		NULL,
	     NULL,					NULL,
	     /* Bonito64 based */
	     NULL,				        NULL,
	     NULL,					NULL );

    if (sys_corecard == MIPS_REVISION_CORID_SEAD_MSC01)
	return;

    syscon_register_id_core( SYSCON_SYSCTRL_PCIREV_MAJOR_ID,
	     /* Galileo based */
	     NULL,				        NULL,
	     NULL,					NULL,
	     /* SysCtrl based */
	     sysctrl_pcirev_maj_msc01_read,		NULL,
	     NULL,					NULL,
	     /* Bonito64 based */
	     NULL,				        NULL,
	     NULL,					NULL );

    syscon_register_id_core( SYSCON_SYSCTRL_PCIREV_MINOR_ID,
	     /* Galileo based */
	     NULL,				        NULL,
	     NULL,					NULL,
	     /* SysCtrl based */
	     sysctrl_pcirev_min_msc01_read,		NULL,
	     NULL,					NULL,
	     /* Bonito64 based */
	     NULL,				        NULL,
	     NULL,					NULL );

    /* PCI parameters */

    syscon_register_generic( SYSCON_CORE_PCI_MEM_START,
	     syscon_uint32_read, (void *)&pci_mem_start,
	     NULL,		 NULL );

    syscon_register_generic( SYSCON_CORE_PCI_MEM_SIZE,
	     syscon_uint32_read, (void *)&pci_mem_size,
	     NULL,		 NULL );

    syscon_register_generic( SYSCON_CORE_PCI_MEM_OFFSET,
	     syscon_uint32_read, (void *)&pci_mem_offset,
	     NULL,		 NULL );

    syscon_register_generic( SYSCON_CORE_PCI_IO_START,
	     syscon_uint32_read, (void *)&pci_io_start,
	     NULL,		 NULL );

    syscon_register_generic( SYSCON_CORE_PCI_IO_SIZE,
	     syscon_uint32_read, (void *)&pci_io_size,
	     NULL,		 NULL );

    syscon_register_generic( SYSCON_CORE_PCI_IO_OFFSET,
	     syscon_uint32_read, (void *)&pci_io_offset,
	     NULL,		 NULL );
}   


/************************************************************************
 *
 *                          syscon_register_id_core
 *  Description :
 *  -------------
 *
 *  Function used to register core card specific SYSCON object functions.
 *
 *  A read and/or write function may be registered for each core card.
 *  A NULL function pointer indicates that the operation (read or
 *  write) is not allowed for the particular platform.
 *
 *  read_data and write_data pointers are passed to the read and write
 *  function.

 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
void 
syscon_register_id_core(
    t_syscon_ids   id,			  /* OBJECT ID from syscon_api.h */

    /* Galileo based */
    t_syscon_func  read_galileo,	  /* Core Galileo read function  */
    void	   *read_data_galileo,	  /* Registered data		 */
    t_syscon_func  write_galileo,	  /* Core Galileo write function */
    void	   *write_data_galileo,   /* Registered data		 */

    /* SysCtrl based */
    t_syscon_func  read_sysctl,	          /* Core SysCtrl read function	 */
    void	   *read_data_sysctl,     /* Registered data		 */
    t_syscon_func  write_sysctl,	  /* Core SysCtrl write function */
    void	   *write_data_sysctl,    /* Registered data		 */

    /* Bonito64 based */
    t_syscon_func  read_bonito64,	  /* Core Bonito64 read          */
    void	   *read_data_bonito64,	  /* Registered data		 */
    t_syscon_func  write_bonito64,	  /* Core Bonito64 write	 */
    void	   *write_data_bonito64 ) /* Registered data		 */
{
    t_syscon_obj *obj;

    obj = &syscon_objects[id];

    switch( sys_corecard )
    {
      case MIPS_REVISION_CORID_CORE_LV :
      case MIPS_REVISION_CORID_CORE_FPGA :
      case MIPS_REVISION_CORID_QED_RM5261 :
      case MIPS_REVISION_CORID_CORE_FPGAr2 :
        obj->read       = read_galileo;
	obj->read_data  = read_data_galileo;
	obj->write      = write_galileo;
	obj->write_data = write_data_galileo;
	break;

      case MIPS_REVISION_CORID_CORE_SYS :
      case MIPS_REVISION_CORID_CORE_FPGA2 :
      case MIPS_REVISION_CORID_CORE_EMUL_SYS :
      case MIPS_REVISION_CORID_SEAD_MSC01 :
        obj->read       = read_sysctl;
	obj->read_data  = read_data_sysctl;
	obj->write      = write_sysctl;
	obj->write_data = write_data_sysctl;
	break;

      case MIPS_REVISION_CORID_BONITO64 :
      case MIPS_REVISION_CORID_CORE_20K :
      case MIPS_REVISION_CORID_CORE_EMUL_20K :
        obj->read       = read_bonito64;
	obj->read_data  = read_data_bonito64;
	obj->write      = write_bonito64;
	obj->write_data = write_data_bonito64;
	break;

      /* Add new core cards here */

      default : /* Should not happen */
        obj->read  = NULL;
	obj->write = NULL;
	break;
    }    
}