📄 syscon_core.c
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void *param, void *data, UINT32 size ){ *(UINT32 *)param = ( BONITO_SDCFG & BONITO_SDCFG_EXTRASCAS ) ? 3 : 2; return OK;}/************************************************************************ * board_systemram_sras2scas_cycles_bonito64_write ************************************************************************/static UINT32board_systemram_sras2scas_cycles_bonito64_write( void *param, void *data, UINT32 size ){ if( *(UINT32 *)param <= 2 ) { sys_func_noram( (t_sys_func_noram)bonito64_write_sdcfg, BONITO_SDCFG & ~BONITO_SDCFG_EXTRASCAS, 0,0 ); } else { sys_func_noram( (t_sys_func_noram)bonito64_write_sdcfg, BONITO_SDCFG | BONITO_SDCFG_EXTRASCAS, 0,0 ); } return OK;}/************************************************************************ * board_systemram_sras2scas_cycles_msc01_read ************************************************************************/static UINT32board_systemram_sras2scas_cycles_msc01_read( void *param, void *data, UINT32 size ){ *(UINT32 *)param = (REG(MSC01_MC_REG_BASE, MSC01_MC_TIMPAR) & MSC01_MC_TIMPAR_TRCD_MSK) >> MSC01_MC_TIMPAR_TRCD_SHF; return OK;}/************************************************************************ * board_systemram_caslat_cycles_gt64120_read ************************************************************************/static UINT32board_systemram_caslat_cycles_gt64120_read( void *param, void *data, UINT32 size ){ UINT32 regval; GT_L32( sys_nb_base, GT_SDRAM_B0_OFS, regval ); switch( REGFIELD( regval, GT_SDRAM_B0_CASLAT ) ) { case GT_SDRAM_B0_CASLAT_2 : *(UINT32 *)param = 2; break; case GT_SDRAM_B0_CASLAT_3 : *(UINT32 *)param = 3; break; default : /* Should not happen */ return ERROR_SYSCON_UNKNOWN_PARAM; } return OK;}/************************************************************************ * board_systemram_caslat_cycles_bonito64_read ************************************************************************/static UINT32board_systemram_caslat_cycles_bonito64_read( void *param, void *data, UINT32 size ){ *(UINT32 *)param = ( BONITO_SDCFG & BONITO_SDCFG_EXTRDDATA ) ? 3 : 2; return OK;}/************************************************************************ * board_systemram_caslat_cycles_msc01_read ************************************************************************/static UINT32board_systemram_caslat_cycles_msc01_read( void *param, void *data, UINT32 size ){ *(UINT32 *)param = (REG(MSC01_MC_REG_BASE, MSC01_MC_LATENCY) & MSC01_MC_LATENCY_CL_MSK) >> MSC01_MC_LATENCY_CL_SHF; return OK;}/************************************************************************ * board_systemram_rw_burstlen_gt64120_read ************************************************************************/static UINT32board_systemram_rw_burstlen_gt64120_read( void *param, void *data, UINT32 size ){ /* Same read and write burstlength */ UINT32 regval; GT_L32( sys_nb_base, GT_SDRAM_B0_OFS, regval ); switch( REGFIELD( regval, GT_SDRAM_B0_BLEN ) ) { case GT_SDRAM_B0_BLEN_4 : *(UINT32 *)param = 4; break; case GT_SDRAM_B0_BLEN_8 : *(UINT32 *)param = 8; break; default : /* Should not happen */ return ERROR_SYSCON_UNKNOWN_PARAM; } return OK;}/************************************************************************ * board_systemram_rw_burstlen_bonito64_read ************************************************************************/static UINT32board_systemram_rw_burstlen_bonito64_read( void *param, void *data, UINT32 size ){ switch( (BONITO_SDCFG & BONITO_SDCFG_DRAMBURSTLEN) >> BONITO_SDCFG_DRAMBURSTLEN_SHIFT ) { case 0 : *(UINT32 *)param = 1; break; case 1 : *(UINT32 *)param = 2; break; case 2 : *(UINT32 *)param = 4; break; default : *(UINT32 *)param = 8; break; } return OK;}/************************************************************************ * board_systemram_rw_burstlen_msc01_read ************************************************************************/static UINT32board_systemram_rw_burstlen_msc01_read( void *param, void *data, UINT32 size ){ *(UINT32 *)param = ( REG(MSC01_MC_REG_BASE, MSC01_MC_HC_DDR) & MSC01_MC_HC_DDR_DDR_BIT ) ? 2 : 1; return OK;}/************************************************************************ * board_systemram_cslat_cycles_msc01_read ************************************************************************/static UINT32board_systemram_cslat_cycles_msc01_read( void *param, void *data, UINT32 size ){ *(UINT32 *)param = (REG(MSC01_MC_REG_BASE, MSC01_MC_LATENCY) & MSC01_MC_LATENCY_CSL_MSK) >> MSC01_MC_LATENCY_CSL_SHF; return OK;}/************************************************************************ * board_systemram_wrlat_cycles_msc01_read ************************************************************************/static UINT32board_systemram_wrlat_cycles_msc01_read( void *param, void *data, UINT32 size ){ *(UINT32 *)param = (REG(MSC01_MC_REG_BASE, MSC01_MC_LATENCY) & MSC01_MC_LATENCY_WL_MSK) >> MSC01_MC_LATENCY_WL_SHF; return OK;}/************************************************************************ * board_systemram_rddel_cycles_msc01_read ************************************************************************/static UINT32board_systemram_rddel_cycles_msc01_read( void *param, void *data, UINT32 size ){ *(UINT32 *)param = (REG(MSC01_MC_REG_BASE, MSC01_MC_HC_RDDEL) & MSC01_MC_HC_RDDEL_RDDEL_MSK) >> MSC01_MC_HC_RDDEL_RDDEL_SHF; return OK;}/************************************************************************ * board_systemram_ddr_msc01_read ************************************************************************/static UINT32board_systemram_ddr_msc01_read( void *param, void *data, UINT32 size ){ *(UINT32 *)param = (REG(MSC01_MC_REG_BASE, MSC01_MC_HC_DDR) & MSC01_MC_HC_DDR_DDR_MSK) >> MSC01_MC_HC_DDR_DDR_SHF; return OK;}/************************************************************************ * board_systemram_fw_msc01_read ************************************************************************/static UINT32board_systemram_fw_msc01_read( void *param, void *data, UINT32 size ){ *(UINT32 *)param = (REG(MSC01_MC_REG_BASE, MSC01_MC_HC_FMDW) & MSC01_MC_HC_FMDW_FMDW_MSK) >> MSC01_MC_HC_FMDW_FMDW_SHF; return OK;}/************************************************************************ * board_systemram_clkrat_msc01_read ************************************************************************/static UINT32board_systemram_clkrat_msc01_read( void *param, void *data, UINT32 size ){ switch (REG(MSC01_MC_REG_BASE, MSC01_MC_HC_CLKRAT)) { case 1: *(char **)param = "1:1"; break; case 2: *(char **)param = "3:2"; break; case 3: *(char **)param = "2:1"; break; case 4: *(char **)param = "3:1"; break; case 5: *(char **)param = "4:1"; break; default: *(char **)param = "unknown"; break; } return OK;}/************************************************************************ * board_systemram_wc_msc01_read * This "performance" bit controls automatic RAM/PCI syncronisation ************************************************************************/static UINT32board_systemram_wc_msc01_read( void *param, void *data, UINT32 size ){ *(UINT32 *)param = (REG(MSC01_BIU_REG_BASE, MSC01_SC_CFG) & MSC01_SC_CFG_WC_MSK) >> MSC01_SC_CFG_WC_SHF; return OK;}/************************************************************************ * sysctrl_sysid_msc01_read ************************************************************************/static UINT32sysctrl_sysid_msc01_read( void *param, void *data, UINT32 size ){ *(UINT32 *)param = REG(MSC01_BIU_REG_BASE, MSC01_SC_SYSID); return OK;}/************************************************************************ * sysctrl_pbcrev_maj_msc01_read ************************************************************************/static UINT32sysctrl_pbcrev_maj_msc01_read( void *param, void *data, UINT32 size ){ *(UINT32 *)param = (REG(MSC01_PBC_REG_BASE, MSC01_PBC_ID) & MSC01_PBC_ID_MAR_MSK) >> MSC01_PBC_ID_MAR_SHF; return OK;}/************************************************************************ * sysctrl_pbcrev_min_msc01_read ************************************************************************/static UINT32sysctrl_pbcrev_min_msc01_read( void *param, void *data, UINT32 size ){ *(UINT32 *)param = (REG(MSC01_PBC_REG_BASE, MSC01_PBC_ID) & MSC01_PBC_ID_MIR_MSK) >> MSC01_PBC_ID_MIR_SHF; return OK;}/************************************************************************ * sysctrl_pcirev_maj_msc01_read ************************************************************************/static UINT32sysctrl_pcirev_maj_msc01_read( void *param, void *data, UINT32 size ){ *(UINT32 *)param = (REG(MSC01_PBC_REG_BASE, MSC01_PCI_ID) & MSC01_PCI_ID_MAR_MSK) >> MSC01_PCI_ID_MAR_SHF; return OK;}/************************************************************************ * sysctrl_pcirev_min_msc01_read ************************************************************************/static UINT32sysctrl_pcirev_min_msc01_read( void *param, void *data, UINT32 size ){ *(UINT32 *)param = (REG(MSC01_PBC_REG_BASE, MSC01_PCI_ID) & MSC01_PCI_ID_MIR_MSK) >> MSC01_PCI_ID_MIR_SHF; return OK;}/************************************************************************ * board_systemram_parity_msc01_read ************************************************************************/static UINT32board_systemram_parity_msc01_read( void *param, void *data, UINT32 size ){ *(UINT32 *)param = (REG(MSC01_MC_REG_BASE, MSC01_MC_HC_PARITY) & MSC01_MC_HC_PARITY_PARITY_MSK) >> MSC01_MC_HC_PARITY_PARITY_SHF; return OK;}/************************************************************************ * board_sysctrl_regaddrbase_generic_read ************************************************************************/static UINT32board_sysctrl_regaddrbase_generic_read( void *param, void *data, UINT32 size ){ *(UINT32 *)param = PHYS( sys_nb_base ); return OK;}/************************************************************************ * Implementation : Public functions ************************************************************************//************************************************************************ * * syscon_arch_core_init * Description : * ------------- * * Initialize core card specific part of SYSCON * * Return values : * --------------- * * None * ************************************************************************/void syscon_arch_core_init( t_syscon_obj *objects, /* Array of SYSCON objects */ UINT32 nb_ram_size, /* Size of MAX RAM range */ UINT32 nb_pci_mem_start, /* PCI memory range start */ UINT32 nb_pci_mem_size, /* PCI memory range size */ UINT32 nb_pci_mem_offset, /* PCI memory range offset */ UINT32 nb_pci_io_start, /* PCI I/O range start */ UINT32 nb_pci_io_size, /* PCI I/O range size */ UINT32 nb_pci_io_offset ) /* PCI I/O range offset */{ UINT32 n; char *s; syscon_objects = objects; ram_range_base = 0; /* RAM must always reside at base address 0 */ if (sys_corecard == MIPS_REVISION_CORID_SEAD_MSC01) goto sead_msc01; /* Special handling of Bonito64 */ if( (sys_corecard == MIPS_REVISION_CORID_BONITO64) || (sys_corecard == MIPS_REVISION_CORID_CORE_20K) || (sys_corecard == MIPS_REVISION_CORID_CORE_EMUL_20K) ) { ram_range_size = BONITO_PCILO_BASE; pci_mem_start = BONITO_PCILO_BASE; pci_mem_size = BONITO_PCILO_SIZE; pci_mem_offset = 0; pci_io_start = 0; pci_io_size = BONITO_PCIIO_SIZE; pci_io_offset = BONITO_PCIIO_BASE; /* System Controller Version String */ for (n = 0; n < 31; n ++) { BONITO_BUILDINFO = n << BONITO_BUILDINFO_ADDR_MASK_SHIFT; version_syscntrl[n] = (char)BONITO_BUILDINFO; } } /* Special handling of System Controller */ else if( sys_corecard == MIPS_REVISION_CORID_CORE_SYS ||⌨️ 快捷键说明
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