📄 syscon_core.c
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/************************************************************************ * * syscon_core.c * * Core card specific parts of SYSCON module. * * ###################################################################### * * mips_start_of_legal_notice * * Copyright (c) 2004 MIPS Technologies, Inc. All rights reserved. * * * Unpublished rights (if any) reserved under the copyright laws of the * United States of America and other countries. * * This code is proprietary to MIPS Technologies, Inc. ("MIPS * Technologies"). Any copying, reproducing, modifying or use of this code * (in whole or in part) that is not expressly permitted in writing by MIPS * Technologies or an authorized third party is strictly prohibited. At a * minimum, this code is protected under unfair competition and copyright * laws. Violations thereof may result in criminal penalties and fines. * * MIPS Technologies reserves the right to change this code to improve * function, design or otherwise. MIPS Technologies does not assume any * liability arising out of the application or use of this code, or of any * error or omission in such code. Any warranties, whether express, * statutory, implied or otherwise, including but not limited to the implied * warranties of merchantability or fitness for a particular purpose, are * excluded. Except as expressly provided in any written license agreement * from MIPS Technologies or an authorized third party, the furnishing of * this code does not give recipient any license to any intellectual * property rights, including any patent rights, that cover this code. * * This code shall not be exported, reexported, transferred, or released, * directly or indirectly, in violation of the law of any country or * international law, regulation, treaty, Executive Order, statute, * amendments or supplements thereto. Should a conflict arise regarding the * export, reexport, transfer, or release of this code, the laws of the * United States of America shall be the governing law. * * This code constitutes one or more of the following: commercial computer * software, commercial computer software documentation or other commercial * items. If the user of this code, or any related documentation of any * kind, including related technical data or manuals, is an agency, * department, or other entity of the United States government * ("Government"), the use, duplication, reproduction, release, * modification, disclosure, or transfer of this code, or any related * documentation of any kind, is restricted in accordance with Federal * Acquisition Regulation 12.212 for civilian agencies and Defense Federal * Acquisition Regulation Supplement 227.7202 for military agencies. The use * of this code by the Government is further restricted in accordance with * the terms of the license agreement(s) and/or applicable contract terms * and conditions covering this code from MIPS Technologies or an authorized * third party. * * * * * mips_end_of_legal_notice * * ************************************************************************//************************************************************************ * Include files ************************************************************************/#include <sysdefs.h>#include <syscon_api.h>#include <sys_api.h>#include <syscon.h>#include <syserror.h>#include <stdio.h>#include <product.h>#include <malta.h>#include <sead.h>#include <gt64120.h>#include <bonito64.h>#include <core_bonito64.h>#include <core_sys.h>#include <pci.h>#include <string.h>/************************************************************************ * Definitions ************************************************************************//************************************************************************ * Public variables ************************************************************************//************************************************************************ * Static variables ************************************************************************//* Pointer to array of objects */static t_syscon_obj *syscon_objects;/* Core card names */static char *name_qed_rm5261 = "QED RM5261 Board";static char *name_core_lv = "CoreLV";static char *name_core_bonito = "CoreBonito64"; /* also "Bonito64" */static char *name_core_20k = "Core20K";static char *name_core_fpga = "CoreFPGA";static char *name_core_sys = "CoreSYS";static char *name_core_emul = "CoreEMUL";static char *name_core_fpga2 = "CoreFPGA-2";static char *name_galileo = "Galileo"; char *name_msc01 = "MIPS SOC-it 101\0 ";static char version_syscntrl[32] = "unknown version";/* North Bridge settings */static UINT32 pci_mem_start;static UINT32 pci_mem_size;static UINT32 pci_mem_offset;static UINT32 pci_io_start;static UINT32 pci_io_size;static UINT32 pci_io_offset;static UINT32 ram_range_base;static UINT32 ram_range_size;/************************************************************************ * Static function prototypes ************************************************************************//************************************************************************ * Static functions ************************************************************************//************************************************************************ * Static functions registered for handling particular SYSCON objects * for particular core cards. ************************************************************************//************************************************************************ * board_systemram_refresh_ns_gt64120_read ************************************************************************/static UINT32board_systemram_refresh_ns_gt64120_read( void *param, void *data, UINT32 size ){ UINT32 regval; GT_L32( sys_nb_base, GT_SDRAM_CFG_OFS, regval); *(UINT32 *)param = CYCLES2NS( REGFIELD( regval, GT_SDRAM_CFG_REFINT ) ); return OK;}/************************************************************************ * board_systemram_refresh_ns_gt64120_write ************************************************************************/static UINT32board_systemram_refresh_ns_gt64120_write( void *param, void *data, UINT32 size ){ UINT32 regval, refcount; NS2COUNT_ROUND_DOWN( *(UINT32 *)param, refcount ); refcount = MIN( refcount, GT_SDRAM_CFG_REFINT_MSK >> GT_SDRAM_CFG_REFINT_SHF ); /* Read */ GT_L32( sys_nb_base, GT_SDRAM_CFG_OFS, regval); /* Modify */ regval &= ~GT_SDRAM_CFG_REFINT_MSK; regval |= (refcount << GT_SDRAM_CFG_REFINT_SHF); /* Write */ sys_func_noram( (t_sys_func_noram)gt64120_write_reg, KSEG1(sys_nb_base + GT_SDRAM_CFG_OFS), regval, 0 ); return OK;}/************************************************************************ * board_systemram_refresh_ns_bonito64_read ************************************************************************/static UINT32board_systemram_refresh_ns_bonito64_read( void *param, void *data, UINT32 size ){ UINT32 mult, clock_ns, cycles_per_refresh; /* Multiply factor (base refresh rate = 3.9 us) */ mult = 1 << ( (BONITO_SDCFG & BONITO_SDCFG_DRAMRFSHMULT) >> BONITO_SDCFG_DRAMRFSHMULT_SHIFT ); /* Bonito64 was informed on CPU clock period */ clock_ns = (BONITO_IODEVCFG & BONITO_IODEVCFG_CPUCLOCKPERIOD) >> BONITO_IODEVCFG_CPUCLOCKPERIOD_SHIFT; if( clock_ns == 0 ) { clock_ns = BONITO_IODEVCFG_CPUCLOCKPERIOD >> BONITO_IODEVCFG_CPUCLOCKPERIOD_SHIFT; } cycles_per_refresh = mult * (UINT32)3900 / clock_ns; *(UINT32 *)param = CYCLES2NS( cycles_per_refresh ); return OK;}/************************************************************************ * board_systemram_refresh_ns_msc01_read ************************************************************************/static UINT32board_systemram_refresh_ns_msc01_read( void *param, void *data, UINT32 size ){ UINT32 count; count = REG(MSC01_MC_REG_BASE, MSC01_MC_TREFRESH); /* adjust count to bus cycles (inverse clk ratio) */ switch (REG(MSC01_MC_REG_BASE, MSC01_MC_HC_CLKRAT)) { case 1: break; case 2: count = (count * 3) / 2; break; case 3: count *= 2; break; case 4: count *= 3; break; case 5: count *= 4; break; } *(UINT32 *)param = CYCLES2NS( count ); return OK;}/************************************************************************ * board_systemram_refresh_ns_msc01_write ************************************************************************/static UINT32board_systemram_refresh_ns_msc01_write( void *param, void *data, UINT32 size ){ UINT32 refcount; NS2COUNT_ROUND_DOWN( *(UINT32 *)param, refcount ); /* adjust from bus cycle count to sdram clock cycle count */ switch (REG(MSC01_MC_REG_BASE, MSC01_MC_HC_CLKRAT)) { case 1: break; case 2: refcount = (refcount * 2) / 3; break; case 3: refcount /= 2; break; case 4: refcount /= 3; break; case 5: refcount /= 4; break; } /* never decrease refresh counter */ if (refcount > REG(MSC01_MC_REG_BASE, MSC01_MC_TREFRESH)) { /* Write */ REG(MSC01_MC_REG_BASE, MSC01_MC_TREFRESH) = refcount; } return OK;}/************************************************************************ * board_systemram_srasprchg_cycles_gt64120_read ************************************************************************/static UINT32board_systemram_srasprchg_cycles_gt64120_read( void *param, void *data, UINT32 size ){ UINT32 regval; GT_L32( sys_nb_base, GT_SDRAM_B0_OFS, regval ); switch( REGFIELD( regval, GT_SDRAM_B0_SRASPRCHG ) ) { case GT_SDRAM_B0_SRASPRCHG_2 : *(UINT32 *)param = 2; break; case GT_SDRAM_B0_SRASPRCHG_3 : *(UINT32 *)param = 3; break; default : /* Should not happen */ return ERROR_SYSCON_UNKNOWN_PARAM; } return OK;}/************************************************************************ * board_systemram_srasprchg_cycles_gt64120_write ************************************************************************/static UINT32board_systemram_srasprchg_cycles_gt64120_write( void *param, void *data, UINT32 size ){ UINT32 regval; /* Read */ GT_L32( sys_nb_base, GT_SDRAM_B0_OFS, regval); /* Modify */ regval &= ~GT_SDRAM_B0_SRASPRCHG_MSK; regval |= ( ( ( *(UINT32 *)param <= 2 ) ? GT_SDRAM_B0_SRASPRCHG_2 : GT_SDRAM_B0_SRASPRCHG_3 ) << GT_SDRAM_B0_SRASPRCHG_SHF ); /* Write */ sys_func_noram( (t_sys_func_noram)gt64120_write_reg, KSEG1(sys_nb_base + GT_SDRAM_B0_OFS), regval, 0 ); return OK;}/************************************************************************ * board_systemram_srasprchg_cycles_bonito64_read ************************************************************************/static UINT32board_systemram_srasprchg_cycles_bonito64_read( void *param, void *data, UINT32 size ){ *(UINT32 *)param = ( BONITO_SDCFG & BONITO_SDCFG_EXTPRECH ) ? 3 : 2; return OK;}/************************************************************************ * board_systemram_srasprchg_cycles_bonito64_write ************************************************************************/static UINT32board_systemram_srasprchg_cycles_bonito64_write( void *param, void *data, UINT32 size ){ if( *(UINT32 *)param <= 2 ) { sys_func_noram( (t_sys_func_noram)bonito64_write_sdcfg, BONITO_SDCFG & ~BONITO_SDCFG_EXTPRECH, 0,0 ); } else { sys_func_noram( (t_sys_func_noram)bonito64_write_sdcfg, BONITO_SDCFG | BONITO_SDCFG_EXTPRECH, 0,0 ); } return OK;}/************************************************************************ * board_systemram_srasprchg_cycles_msc01_read ************************************************************************/static UINT32board_systemram_srasprchg_cycles_msc01_read( void *param, void *data, UINT32 size ){ *(UINT32 *)param = (REG(MSC01_MC_REG_BASE, MSC01_MC_TIMPAR) & MSC01_MC_TIMPAR_TRP_MSK) >> MSC01_MC_TIMPAR_TRP_SHF; return OK;}/************************************************************************ * board_systemram_sras2scas_cycles_gt64120_read ************************************************************************/static UINT32board_systemram_sras2scas_cycles_gt64120_read( void *param, void *data, UINT32 size ){ UINT32 regval; GT_L32( sys_nb_base, GT_SDRAM_B0_OFS, regval ); switch( REGFIELD( regval, GT_SDRAM_B0_SRAS2SCAS ) ) { case GT_SDRAM_B0_SRAS2SCAS_2 : *(UINT32 *)param = 2; break; case GT_SDRAM_B0_SRAS2SCAS_3 : *(UINT32 *)param = 3; break; default : /* Should not happen */ return ERROR_SYSCON_UNKNOWN_PARAM; } return OK;}/************************************************************************ * board_systemram_sras2scas_cycles_gt64120_write ************************************************************************/static UINT32board_systemram_sras2scas_cycles_gt64120_write( void *param, void *data, UINT32 size ){ UINT32 regval; /* Read */ GT_L32( sys_nb_base, GT_SDRAM_B0_OFS, regval); /* Modify */ regval &= ~GT_SDRAM_B0_SRAS2SCAS_MSK; regval |= ( ( ( *(UINT32 *)param <= 2 ) ? GT_SDRAM_B0_SRAS2SCAS_2 : GT_SDRAM_B0_SRAS2SCAS_3 ) << GT_SDRAM_B0_SRAS2SCAS_SHF ); /* Write */ sys_func_noram( (t_sys_func_noram)gt64120_write_reg, KSEG1(sys_nb_base + GT_SDRAM_B0_OFS), regval, 0 ); return OK;}/************************************************************************ * board_systemram_sras2scas_cycles_bonito64_read ************************************************************************/static UINT32board_systemram_sras2scas_cycles_bonito64_read(⌨️ 快捷键说明
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