syscon_cpu.c

sigma yamon yamon-src-02[1].06.tar.gz

cpu_read_cp0(
    void   *param,
    void   *data,
    UINT32 size )
{
    t_syscon_cp0_reg *def = (t_syscon_cp0_reg *)data;
  
    if(!def->valid)
        return ERROR_SYSCON_UNKNOWN_PARAM;

    if( size == sizeof(UINT32) )
    {
	*(UINT32 *)param = sys_cp0_read32( def->number, def->sel );
	return OK;
    }
    else if( size == sizeof(UINT64) )
    {
        if( def->regsize == sizeof(UINT32) )
	    *(INT64 *)param = (INT64)sys_cp0_read32( def->number, def->sel );
	else
	    *(INT64 *)param =        sys_cp0_read64( def->number, def->sel );

	return OK;
    }
    else
	return ERROR_SYSCON_SIZE_MISMATCH;
}


/************************************************************************
 *  cpu_write_cp0
 *  OBS: The size argument is buffer size - NOT register width
 ************************************************************************/
static UINT32
cpu_write_cp0(
    void   *param,
    void   *data,
    UINT32 size )
{
    t_syscon_cp0_reg *def = (t_syscon_cp0_reg *)data;
  
    if(!def->valid)
        return ERROR_SYSCON_UNKNOWN_PARAM;

    if( size == sizeof(UINT32) )
    {
        if( def->regsize == sizeof(UINT32) )
            sys_cp0_write32( def->number, def->sel,               *(UINT32 *)param );
	else
            sys_cp0_write64( def->number, def->sel, (UINT64)(INT64)*(INT32 *)param );

	return OK;
    }
    else if( size == sizeof(UINT64) )
    {
        if( def->regsize == sizeof(UINT32) )
            sys_cp0_write32( def->number, def->sel, (UINT32)*(UINT64 *)param );
	else
            sys_cp0_write64( def->number, def->sel,         *(UINT64 *)param );

	return OK;
    }
    else
	return ERROR_SYSCON_SIZE_MISMATCH;
}


/************************************************************************
 *  cpu_cp0_config1_reset_mips32_read
 ************************************************************************/
static UINT32
cpu_cp0_config1_reset_mips32_read(
    void   *param,
    void   *data,
    UINT32 size )
{
    *(UINT32 *)param = config1_init;
    return OK;
}


/************************************************************************
 *  cpu_tlb_count_mips32_read
 ************************************************************************/
static UINT32
cpu_tlb_count_mips32_read(
    void   *param,
    void   *data,
    UINT32 size )
{
    UINT32 config1;
  
    SYSCON_read(
        SYSCON_CPU_CP0_CONFIG1_ID,
        (void *)&config1,
	sizeof(UINT32) );	

    *(UINT8 *)param = 
        (( config1 & M_Config1MMUSize ) >> S_Config1MMUSize) + 1;
    return OK;
}


/************************************************************************
 *  cpu_tlb_count_rm5261_read
 ************************************************************************/
static UINT32
cpu_tlb_count_rm5261_read(
    void   *param,
    void   *data,
    UINT32 size )
{
    *(UINT8 *)param = 
        (sys_processor == QED_RM52XX) ?
	    QED_RM52XX_TLB_ENTRIES :
	    QED_RM70XX_TLB_ENTRIES;

    return OK;
}


/************************************************************************
 *  Implementation : Public functions
 ************************************************************************/


/************************************************************************
 *
 *                          syscon_arch_cpu_init
 *  Description :
 *  -------------
 *
 *  Initialize cpu specific part of SYSCON
 *
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
void 
syscon_arch_cpu_init( 
    t_syscon_obj *objects )		/* Array of SYSCON objects	*/
{
    UINT32 mask;
    UINT32 config, config1, config2, config3, ctrl;
    bool   tag_data, lladdr, watch, trace, cacheerr, errctl;
    UINT32 i;
    
    syscon_objects = objects;

    /* CP0 registers */
    for(i=0;i<SYSCON_CP0_REG_COUNT;i++)
    {
        syscon_register_generic(
	    cp0_reg[i].id,
	    cpu_read_cp0,  (void *)&(cp0_reg[i]),
	    cpu_write_cp0, (void *)&(cp0_reg[i]) );
    }

    switch( sys_processor )
    {
      case MIPS_25Kf  :

	cp0_reg[SYSCON_L23TAGLO ].valid = TRUE;
	cp0_reg[SYSCON_L23DATALO].valid = TRUE;
	cp0_reg[SYSCON_L23TAGHI ].valid = TRUE;
	cp0_reg[SYSCON_L23DATAHI].valid = TRUE;

        /* Fallthrough !! */

      case MIPS_20Kc  :

        cp0_reg[SYSCON_DERRCTL].valid = TRUE;
	cp0_reg[SYSCON_IERRCTL].valid = TRUE;
	cp0_reg[SYSCON_ITAGLO ].valid = TRUE;
	cp0_reg[SYSCON_IDATALO].valid = TRUE;
	cp0_reg[SYSCON_DTAGLO ].valid = TRUE;
	cp0_reg[SYSCON_DDATALO].valid = TRUE;
	cp0_reg[SYSCON_ITAGHI ].valid = TRUE;
	cp0_reg[SYSCON_IDATAHI].valid = TRUE;
	cp0_reg[SYSCON_DTAGHI ].valid = TRUE;
	cp0_reg[SYSCON_DDATAHI].valid = TRUE;

	goto common;

      case MIPS_24K :

	cp0_reg[SYSCON_L23TAGLO ].valid = TRUE;
	cp0_reg[SYSCON_ITAGLO ].valid   = TRUE;
	cp0_reg[SYSCON_IDATALO].valid   = TRUE;
	cp0_reg[SYSCON_IDATAHI].valid   = TRUE;
	cp0_reg[SYSCON_DTAGLO ].valid   = TRUE;
	cp0_reg[SYSCON_DDATALO].valid   = TRUE;

        goto common;

common:

      case MIPS_4Kc      :
      case MIPS_4Kmp     :
      case MIPS_4KEc     :
      case MIPS_4KEc_R2  :
      case MIPS_4KEmp    :
      case MIPS_4KEmp_R2 :
      case MIPS_4KSc     :
      case MIPS_4KSd     :
      case MIPS_M4K      :
      case MIPS_5K       :
      case MIPS_5KE      :

        /* Store initial setting of CP0 CONFIG1 register */
	config1      = sys_cp0_read32( R_C0_Config, R_C0_SelConfig1 );
	config1_init = config1;

        /* Detect whether cache/TLB is configurable */

        /*  This feature is present specifically to support configuration
         *  testing of the core in a lead vehicle, and is not supported
         *  in any other environment.  Attempting to use this feature
         *  outside of the scope of a lead vehicle is a violation of the
         *  MIPS Architecture, and may cause unpredictable operation of
         *  the processor.
         */

        mask = sys_cpu_configurability();

        cache_configurable = 
            (mask & SYS_CPU_CONFIGURABILITY_CACHE) ? 
                TRUE : FALSE;

        mmu_configurable = 
            (mask & SYS_CPU_CONFIGURABILITY_MMU) ? 
	        TRUE : FALSE;

	config = sys_cp0_read32( R_C0_Config, R_C0_SelConfig );

	/* TLB availability */
	tlb = 
	    ( (config & M_ConfigMT) >> S_ConfigMT == K_ConfigMT_TLBMMU ) ?
	        TRUE : FALSE;

        /* Watch */
	watch =
	    (config1 & M_Config1WR) ?
	        TRUE : FALSE;

	/* TagHi, TagLo, DataHi, DataLo */
        tag_data = 
          ( sys_processor != MIPS_20Kc ) &&
          ( sys_processor != MIPS_25Kf ) &&
	  ( sys_processor != MIPS_24K  ) &&
          ( sys_processor != MIPS_M4K  );

	/* LLAddr */
	lladdr = 
	  ( sys_processor != MIPS_M4K ) &&
	  ( sys_processor != MIPS_5K  ) &&
	  ( sys_processor != MIPS_5KE ) &&
	  ( sys_processor != MIPS_24K );

	/* CacheErr */
	cacheerr =
	  ( sys_processor != MIPS_4Kc      ) &&
	  ( sys_processor != MIPS_4Kmp     ) &&
	  ( sys_processor != MIPS_4KEc     ) &&
	  ( sys_processor != MIPS_4KEc_R2  ) &&
	  ( sys_processor != MIPS_4KEmp    ) &&
	  ( sys_processor != MIPS_4KEmp_R2 ) &&
	  ( sys_processor != MIPS_4KSc     ) &&
	  ( sys_processor != MIPS_4KSd     ) &&
	  ( sys_processor != MIPS_M4K      );

	/* ErrCtl */
	errctl =
          ( sys_processor != MIPS_20Kc ) &&
          ( sys_processor != MIPS_25Kf ) &&
          ( sys_processor != MIPS_M4K  );

	/* Release 2 */
        if( sys_arch_rev >= K_ConfigAR_Rel2 )
	{
            cp0_reg[SYSCON_PAGEGRAIN].valid = ( sys_processor != MIPS_24K ) ? TRUE : FALSE;
            cp0_reg[SYSCON_HWRENA   ].valid = TRUE;
            cp0_reg[SYSCON_EBASE    ].valid = TRUE;
            cp0_reg[SYSCON_INTCTL   ].valid = TRUE;
            cp0_reg[SYSCON_SRSCTL   ].valid = TRUE;
            cp0_reg[SYSCON_SRSMAP   ].valid = TRUE;
        }

	/* EJTAG */
	cp0_reg[SYSCON_DEBUG    ].valid = sys_ejtag;
	cp0_reg[SYSCON_DEPC     ].valid = sys_ejtag;
	cp0_reg[SYSCON_DESAVE   ].valid = sys_ejtag;