__projnav.log

I2C接口的源码测试程序、Verilog语言编写

Project Navigator Auto-Make Log File
-------------------------------------




Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "i2c_master_bit_ctrl.v"
Compiling include file "i2c_master_defines.v"
Module <i2c_master_bit_ctrl> compiled
Compiling source file "i2c_master_byte_ctrl.v"
Compiling include file "i2c_master_defines.v"
WARNING:HDLCompilers:38 - i2c_master_defines.v line 60 Macro 'I2C_CMD_NOP' redefined
WARNING:HDLCompilers:38 - i2c_master_defines.v line 61 Macro 'I2C_CMD_START' redefined
WARNING:HDLCompilers:38 - i2c_master_defines.v line 62 Macro 'I2C_CMD_STOP' redefined
WARNING:HDLCompilers:38 - i2c_master_defines.v line 63 Macro 'I2C_CMD_WRITE' redefined
WARNING:HDLCompilers:38 - i2c_master_defines.v line 64 Macro 'I2C_CMD_READ' redefined
Module <i2c_master_byte_ctrl> compiled
Compiling source file "i2c_master_top.v"
Compiling include file "i2c_master_defines.v"
WARNING:HDLCompilers:38 - i2c_master_defines.v line 60 Macro 'I2C_CMD_NOP' redefined
WARNING:HDLCompilers:38 - i2c_master_defines.v line 61 Macro 'I2C_CMD_START' redefined
WARNING:HDLCompilers:38 - i2c_master_defines.v line 62 Macro 'I2C_CMD_STOP' redefined
WARNING:HDLCompilers:38 - i2c_master_defines.v line 63 Macro 'I2C_CMD_WRITE' redefined
WARNING:HDLCompilers:38 - i2c_master_defines.v line 64 Macro 'I2C_CMD_READ' redefined
Module <i2c_master_top> compiled
No errors in compilation
Analysis of file <i2c_master_top.prj> succeeded.
 
Completed process "Check Syntax".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "i2c_master_bit_ctrl.v"
Compiling include file "i2c_master_defines.v"
Module <i2c_master_bit_ctrl> compiled
No errors in compilation
Analysis of file <i2c_master_bit_ctrl.prj> succeeded.
 
Completed process "Check Syntax".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "i2c_master_bit_ctrl.v"
Compiling include file "i2c_master_defines.v"
Module <i2c_master_bit_ctrl> compiled
No errors in compilation
Analysis of file <i2c_master_bit_ctrl.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <i2c_master_bit_ctrl>.
WARNING:Xst:916 - i2c_master_bit_ctrl.v line 180: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_master_bit_ctrl.v line 189: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_master_bit_ctrl.v line 190: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_master_bit_ctrl.v line 194: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_master_bit_ctrl.v line 195: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
Module <i2c_master_bit_ctrl> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <i2c_master_bit_ctrl>.
    Related source file is i2c_master_bit_ctrl.v.
    Found finite state machine <FSM_0> for signal <c_state>.
    -----------------------------------------------------------------------
    | States             | 18                                             |
    | Transitions        | 50                                             |
    | Inputs             | 6                                              |
    | Outputs            | 19                                             |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $n0001 (positive)                              |
    | Reset              | nReset (negative)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000000000000000001                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <sda_oen>.
    Found 1-bit register for signal <al>.
    Found 1-bit register for signal <cmd_ack>.
    Found 1-bit register for signal <busy>.
    Found 1-bit register for signal <scl_oen>.
    Found 1-bit register for signal <dout>.
    Found 16-bit subtractor for signal <$n0049> created at line 210.
    Found 1-bit register for signal <clk_en>.
    Found 1-bit register for signal <cmd_stop>.
    Found 16-bit register for signal <cnt>.
    Found 1-bit register for signal <dcmd_stop>.
    Found 1-bit register for signal <dSCL>.
    Found 1-bit register for signal <dscl_oen>.
    Found 1-bit register for signal <dSDA>.
    Found 1-bit register for signal <sda_chk>.
    Found 1-bit register for signal <sSCL>.
    Found 1-bit register for signal <sSDA>.
    Found 1-bit register for signal <sta_condition>.
    Found 1-bit register for signal <sto_condition>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  33 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <i2c_master_bit_ctrl> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Registers                        : 18
  1-bit register                   : 17
  16-bit register                  : 1
# Adders/Subtractors               : 1
  16-bit subtractor                : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <c_state> with one-hot encoding.

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <i2c_master_bit_ctrl> ...
Loading device for application Xst from file '2s50e.nph' in environment C:/Program Files/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block i2c_master_bit_ctrl, actual ratio is 7.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50etq144-6 

 Number of Slices:                      59  out of    768     7%  
 Number of Slice Flip Flops:            51  out of   1536     3%  
 Number of 4 input LUTs:               103  out of   1536     6%  
 Number of bonded IOBs:                 34  out of    102    33%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 51    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 11.421ns (Maximum Frequency: 87.558MHz)
   Minimum input arrival time before clock: 9.040ns
   Maximum output required time after clock: 8.619ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "i2c_master_bit_ctrl.v"
Compiling include file "i2c_master_defines.v"
Module <i2c_master_bit_ctrl> compiled
Compiling source file "i2c_master_byte_ctrl.v"