📄 rtl8139hw.h
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/****************************************************************************
2004.12 第十项目小组
主编：王翔 徐隽
协助：卢坚 夏亮 傅佳伟 郑皓 黄君炜
测试：王弥
Rtl8139 根据 Win2000 DDK提供的Network Samples框架基础上进行编码
（声明：本驱动程序仅用于学习、探索、实践计算机网络相关知识之用。
请勿在未征得本小组同意的情况下随意传播。对使用本程序可能造成的
硬件问题本小组概不负责。也请勿将它用于学习之外的任何用途，本小组
对此种行为可能造成的不良后果概不负责。）
****************************************************************************/
/*++
模块名:
RTL8139hw.h
概要:
定义硬件相关信息
--*/
#ifndef _RTL8139HW_
#define _RTL8139HW_
#define PCIBUS 5
#define AE2_ADAPTER_ID 0x67b0
#define UB_ADAPTER_ID 0x611f
#define NE2_ADAPTER_ID 0x7154
#define MC_IRQ_MASK 0x60
#define MC_IRQ_MASK_UB 0x0E
#define MC_IO_BASE_MASK 0x0E
#define MC_IO_BASE_MASK_UB 0xE0
#define CIS_NET_ADDR_OFFSET 0xff0
#define DEFAULT_MULTICASTLISTMAX 8
#define NIC_COMMAND 0x0 // (CR)
#define NIC_PAGE_START 0x1 // (PSTART) MSB, write-only
#define NIC_PHYS_ADDR 0x1 // (PAR0) page 1
#define NIC_PAGE_STOP 0x2 // (PSTOP) MSB, write-only
#define NIC_BOUNDARY 0x3 // (BNRY) MSB
#define NIC_XMIT_START 0x4 // (TPSR) MSB, write-only
#define NIC_XMIT_STATUS 0x4 // (TSR) read-only
#define NIC_XMIT_COUNT_LSB 0x5 // (TBCR0) write-only
#define NIC_XMIT_COUNT_MSB 0x6 // (TBCR1) write-only
#define NIC_FIFO 0x6 // (FIFO) read-only
#define NIC_INTR_STATUS 0x7 // (ISR)
#define NIC_CURRENT 0x7 // (CURR) page 1
#define NIC_MC_ADDR 0x8 // (MAR0) page 1
#define NIC_CRDA_LSB 0x8 // (CRDA0)
#define NIC_RMT_ADDR_LSB 0x8 // (RSAR0)
#define NIC_CRDA_MSB 0x9 // (CRDA1)
#define NIC_RMT_ADDR_MSB 0x9 // (RSAR1)
#define NIC_RMT_COUNT_LSB 0xa // (RBCR0) write-only
#define NIC_RMT_COUNT_MSB 0xb // (RBCR1) write-only
#define NIC_RCV_CONFIG 0xc // (RCR) write-only
#define NIC_RCV_STATUS 0xc // (RSR) read-only
#define NIC_XMIT_CONFIG 0xd // (TCR) write-only
#define NIC_FAE_ERR_CNTR 0xd // (CNTR0) read-only
#define NIC_DATA_CONFIG 0xe // (DCR) write-only
#define NIC_CRC_ERR_CNTR 0xe // (CNTR1) read-only
#define NIC_INTR_MASK 0xf // (IMR) write-only
#define NIC_MISSED_CNTR 0xf // (CNTR2) read-only
#define NIC_RACK_NIC 0x10 //
#define NIC_RESET 0x1f // (RESET)
#define CR_STOP (UCHAR)0x01
#define CR_START (UCHAR)0x02
#define CR_XMIT (UCHAR)0x04
#define CR_NO_DMA (UCHAR)0x20
#define CR_PS0 (UCHAR)0x40
#define CR_PS1 (UCHAR)0x80
#define CR_PAGE0 (UCHAR)0x00
#define CR_PAGE1 CR_PS0
#define CR_PAGE2 CR_PS1
#define CR_DMA_WRITE (UCHAR)0x10
#define CR_DMA_READ (UCHAR)0x08
#define CR_SEND (UCHAR)0x18
#define TSR_XMIT_OK (UCHAR)0x01
#define TSR_COLLISION (UCHAR)0x04
#define TSR_ABORTED (UCHAR)0x08
#define TSR_NO_CARRIER (UCHAR)0x10
#define TSR_NO_CDH (UCHAR)0x40
#define ISR_EMPTY (UCHAR)0x00
#define ISR_RCV (UCHAR)0x01
#define ISR_XMIT (UCHAR)0x02
#define ISR_RCV_ERR (UCHAR)0x04
#define ISR_XMIT_ERR (UCHAR)0x08
#define ISR_OVERFLOW (UCHAR)0x10
#define ISR_COUNTER (UCHAR)0x20
#define ISR_DMA_DONE (UCHAR)0x40
#define ISR_RESET (UCHAR)0x80
#define RCR_REJECT_ERR (UCHAR)0x00
#define RCR_BROADCAST (UCHAR)0x04
#define RCR_MULTICAST (UCHAR)0x08
#define RCR_ALL_PHYS (UCHAR)0x10
#define RCR_MONITOR (UCHAR)0x20
#define RSR_PACKET_OK (UCHAR)0x01
#define RSR_CRC_ERROR (UCHAR)0x02
#define RSR_MULTICAST (UCHAR)0x20
#define RSR_DISABLED (UCHAR)0x40
#define RSR_DEFERRING (UCHAR)0x80
#define TCR_NO_LOOPBACK (UCHAR)0x00
#define TCR_LOOPBACK (UCHAR)0x02
#define TCR_INHIBIT_CRC (UCHAR)0x01
#define TCR_NIC_LBK (UCHAR)0x02
#define TCR_SNI_LBK (UCHAR)0x04
#define TCR_COAX_LBK (UCHAR)0x06
#define DCR_BYTE_WIDE (UCHAR)0x00
#define DCR_WORD_WIDE (UCHAR)0x01
#define DCR_LOOPBACK (UCHAR)0x00
#define DCR_NORMAL (UCHAR)0x08
#define DCR_FIFO_2_BYTE (UCHAR)0x00
#define DCR_FIFO_4_BYTE (UCHAR)0x20
#define DCR_FIFO_8_BYTE (UCHAR)0x40
#define DCR_FIFO_12_BYTE (UCHAR)0x60
#define DCR_AUTO_INIT (UCHAR)0x10
#define IMR_RCV (UCHAR)0x01
#define IMR_XMIT (UCHAR)0x02
#define IMR_RCV_ERR (UCHAR)0x04
#define IMR_XMIT_ERR (UCHAR)0x08
#define IMR_OVERFLOW (UCHAR)0x10
#define IMR_COUNTER (UCHAR)0x20
#define BIT_0 0x0001
#define BIT_1 0x0002
#define BIT_2 0x0004
#define BIT_3 0x0008
#define BIT_4 0x0010
#define BIT_5 0x0020
#define BIT_6 0x0040
#define BIT_7 0x0080
#define BIT_8 0x0100
#define BIT_9 0x0200
#define BIT_10 0x0400
#define BIT_11 0x0800
#define BIT_12 0x1000
#define BIT_13 0x2000
#define BIT_14 0x4000
#define BIT_15 0x8000
#define BIT_24 0x01000000
#define BIT_28 0x10000000
#define BIT_0_2 0x0007
#define BIT_0_3 0x000F
#define BIT_0_4 0x001F
#define BIT_0_5 0x003F
#define BIT_0_6 0x007F
#define BIT_0_7 0x00FF
#define BIT_0_8 0x01FF
#define BIT_0_13 0x3FFF
#define BIT_0_15 0xFFFF
#define BIT_1_2 0x0006
#define BIT_1_3 0x000E
#define BIT_2_5 0x003C
#define BIT_3_4 0x0018
#define BIT_4_5 0x0030
#define BIT_4_6 0x0070
#define BIT_4_7 0x00F0
#define BIT_5_7 0x00E0
#define BIT_5_9 0x03E0
#define BIT_5_12 0x1FE0
#define BIT_5_15 0xFFE0
#define BIT_6_7 0x00c0
#define BIT_7_11 0x0F80
#define BIT_8_10 0x0700
#define BIT_9_13 0x3E00
#define BIT_12_15 0xF000
#define BIT_16_20 0x001F0000
#define BIT_21_25 0x03E00000
#define BIT_26_27 0x0C000000
#define CMD_IO_SPACE BIT_0
#define CMD_MEMORY_SPACE BIT_1
#define CMD_BUS_MASTER BIT_2
#define CMD_SPECIAL_CYCLES BIT_3
#define CMD_MEM_WRT_INVALIDATE BIT_4
#define CMD_VGA_PALLETTE_SNOOP BIT_5
#define CMD_PARITY_RESPONSE BIT_6
#define CMD_WAIT_CYCLE_CONTROL BIT_7
#define CMD_SERR_ENABLE BIT_8
#define CMD_BACK_TO_BACK BIT_9
#define PCI_VENDOR_ID_REGISTER 0x00
#define PCI_REV_ID_REGISTER 0x08
#define PCI_SUBVENDOR_ID_REGISTER 0x2c
#define PCI_COMMAND_REGISTER 0x04
#define CardStart(Adapter) \
NdisRawWritePortUchar(((Adapter->IoAddr)+NIC_XMIT_CONFIG), TCR_NO_LOOPBACK)
#define CardSetAllMulticast(Adapter) \
NdisMSynchronizeWithInterrupt(&(Adapter)->Interrupt, \
SyncCardSetAllMulticast, (PVOID)(Adapter))
#define CardCopyMulticastRegs(Adapter) \
NdisMSynchronizeWithInterrupt(&(Adapter)->Interrupt, \
SyncCardCopyMulticastRegs, (PVOID)(Adapter))
#define CardGetInterruptStatus(_Adapter,_InterruptStatus) \
NdisRawReadPortUchar(((_Adapter)->IoAddr+NIC_INTR_STATUS), (_InterruptStatus))
#define CardSetReceiveConfig(Adapter) \
NdisMSynchronizeWithInterrupt(&(Adapter)->Interrupt, \
SyncCardSetReceiveConfig, (PVOID)(Adapter))
#define CardBlockInterrupts(Adapter) \
NdisRawWritePortUchar(((Adapter)->IoAddr+NIC_INTR_MASK), 0)
#define CardUnblockInterrupts(Adapter) \
NdisRawWritePortUchar(\
((Adapter)->IoAddr+NIC_INTR_MASK), \
(Adapter)->NicInterruptMask)
#define CardAcknowledgeOverflowInterrupt(Adapter) \
SyncCardAcknowledgeOverflow(Adapter)
#define CardAcknowledgeCounterInterrupt(Adapter) \
NdisRawWritePortUchar(((Adapter)->IoAddr+NIC_INTR_STATUS), ISR_COUNTER)
#define CardUpdateCounters(Adapter) \
NdisMSynchronizeWithInterrupt(&(Adapter)->Interrupt, \
SyncCardUpdateCounters, (PVOID)(Adapter))
#endif //
#define PCI_VENDOR_ID 0x00 /* 16 bits */
#define PCI_DEVICE_ID 0x02 /* 16 bits */
#define PCI_COMMAND 0x04 /* 16 bits */
#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
#define PCI_STATUS 0x06 /* 16 bits */
#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
#define PCI_STATUS_DEVSEL_FAST 0x000
#define PCI_STATUS_DEVSEL_MEDIUM 0x200
#define PCI_STATUS_DEVSEL_SLOW 0x400
#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
revision */
#define PCI_REVISION_ID 0x08 /* Revision ID */
#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
#define PCI_CLASS_DEVICE 0x0a /* Device class */
#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
#define PCI_HEADER_TYPE 0x0e /* 8 bits */
#define PCI_HEADER_TYPE_NORMAL 0
#define PCI_HEADER_TYPE_BRIDGE 1
#define PCI_HEADER_TYPE_CARDBUS 2
#define PCI_BIST 0x0f /* 8 bits */
#define PCI_BIST_CODE_MASK 0x0f /* Return result */
#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
enum RTL8139_registers {
MAC0 = 0,
MAR0 = 8,
TxStatus0 = 0x10,
TxAddr0 = 0x20,
RxBuf = 0x30,
RxEarlyCnt = 0x34,
RxEarlyStatus = 0x36,
ChipCmd = 0x37,
RxBufPtr = 0x38,
RxBufAddr = 0x3A,
IntrMask = 0x3C,
IntrStatus = 0x3E,
TxConfig = 0x40,
ChipVersion = 0x43,
RxConfig = 0x44,
Timer = 0x48,
RxMissed = 0x4C,
Cfg9346 = 0x50,
Config0 = 0x51,
Config1 = 0x52,
FlashReg = 0x54,
MediaStatus = 0x58,
Config3 = 0x59,
Config4 = 0x5A,
HltClk = 0x5B,
MultiIntr = 0x5C,
TxSummary = 0x60,
BasicModeCtrl = 0x62,
BasicModeStatus = 0x64,
NWayAdvert = 0x66,
NWayLPAR = 0x68,
NWayExpansion = 0x6A,
FIFOTMS = 0x70,
CSCR = 0x74,
PARA78 = 0x78,
PARA7c = 0x7c,
Config5 = 0xD8,
};
enum ChipCmdBits {
CmdReset = 0x10,
CmdRxEnb = 0x08,
CmdTxEnb = 0x04,
RxBufEmpty = 0x01,
};
enum Config1Bits {
Cfg1_PM_Enable = 0x01,
Cfg1_VPD_Enable = 0x02,
Cfg1_PIO = 0x04,
Cfg1_MMIO = 0x08,
LWAKE = 0x10,
Cfg1_Driver_Load = 0x20,
Cfg1_LED0 = 0x40,
Cfg1_LED1 = 0x80,
SLEEP = (1 << 1),
PWRDN = (1 << 0),
};
enum IntrStatusBits {
PCIErr = 0x8000,
PCSTimeout = 0x4000,
RxFIFOOver = 0x40,
RxUnderrun = 0x20,
RxOverflow = 0x10,
TxErr = 0x08,
TxOK = 0x04,
RxErr = 0x02,
RxOK = 0x01,
};
enum TxStatusBits {
TxHostOwns = 0x2000,
TxUnderrun = 0x4000,
TxStatOK = 0x8000,
TxOutOfWindow = 0x20000000,
TxAborted = 0x40000000,
TxCarrierLost = 0x80000000,
};
enum RxStatusBits {
RxMulticast = 0x8000,
RxPhysical = 0x4000,
RxBroadcast = 0x2000,
RxBadSymbol = 0x0020,
RxRunt = 0x0010,
RxTooLong = 0x0008,
RxCRCErr = 0x0004,
RxBadAlign = 0x0002,
RxStatusOK = 0x0001,
};
#define rtl8139_rx_config \
RxCfgEarlyRxNone | RxCfgRcv16K | RxNoWrap |(AcceptMyPhys | AcceptBroadcast | AcceptMulticast) | \
(RX_FIFO_THRESH << RxCfgFIFOShift) | \
(RX_DMA_BURST << RxCfgDMAShift)
enum rx_mode_bits {
AcceptErr = 0x20,
AcceptRunt = 0x10,
AcceptBroadcast = 0x08,
AcceptMulticast = 0x04,
AcceptMyPhys = 0x02,
AcceptAllPhys = 0x01,
};
#define RX_FIFO_THRESH 2
#define RX_DMA_BURST 4
#define TX_DMA_BURST 4
enum RxConfigBits {
RxCfgEarlyRxNone = 0,
RxCfgEarlyRxShift = 24,
RxCfgFIFOShift = 13,
RxCfgFIFONone = (7 << RxCfgFIFOShift),
RxCfgDMAShift = 8,
RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
RxCfgRcv8K = 0,
RxCfgRcv16K = (1 << 11),
RxCfgRcv32K = (1 << 12),
RxCfgRcv64K = (1 << 11) | (1 << 12),
RxNoWrap = (1 << 7),
};
#define RL_TXCFG_CONFIG (TX_DMA_BURST << TxDMAShift)|TxIFG1|TxIFG0
enum tx_config_bits {
TxIFG1 = (1 << 25),
TxIFG0 = (1 << 24),
TxLoopBack = (1 << 18) | (1 << 17),
TxCRC = (1 << 16),
TxClearAbt = (1 << 0),
TxDMAShift = 8,
TxVersionMask = 0x7C800000,
};
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