hawaii_include.h

CAN转232总线的单片机程序(AVR实现)

 
/* EEPROM Control Register - EECR */
#define    EERIE    3
#define    EEMWE    2
#define    EEWE     1
#define    EERE     0

/* Special Function I/O Register - SFIOR */
#define    TSM      7
#define    ADHSM    4
#define    ACME     3
#define    PUD      2
#define    PSR0     1
#define    PSR321   0

/* Watchdog Timer Control Register - WDTCR */
#define    WDCE     4
#define    WDE      3
#define    WDP2     2
#define    WDP1     1
#define    WDP0     0

/* On-Chip Debug Register - OCDR */
#define    IDRD     7
#define    OCDR6    6
#define    OCDR5    5
#define    OCDR4    4
#define    OCDR3    3
#define    OCDR2    2
#define    OCDR1    1
#define    OCDR0    0

/* Timer/Counter2 Control Register - TCCR2 */
#define    FOC2     7
#define    WGM20    6
#define    COM21    5
#define    COM20    4
#define    WGM21    3
#define    CS22     2
#define    CS21     1
#define    CS20     0

/* Timer/Counter1 Control Register B - TCCR1B */
#define    ICNC1    7
#define    ICES1    6
#define    WGM13    4
#define    WGM12    3
#define    CS12     2
#define    CS11     1
#define    CS10     0

/* Timer/Counter1 Control Register A - TCCR1A */
#define    COM1A1   7
#define    COM1A0   6
#define    COM1B1   5
#define    COM1B0   4
#define    COM1C1   3
#define    COM1C0   2
#define    WGM11    1
#define    WGM10    0

/* Asynchronous Status Register - ASSR */
#define    AS0      3
#define    TCN0UB   2
#define    OCR0UB   1
#define    TCR0UB   0

/* Timer/Counter0 Control Register - TCCR0 */
#define    FOC0     7
#define    WGM00    6
#define    COM01    5
#define    COM00    4
#define    WGM01    3
#define    CS02     2
#define    CS01     1
#define    CS00     0

/* MCU Control and Status Register - MCUCSR */
#define    JTD      7
#define    JTRF     4
#define    WDRF     3
#define    BORF     2
#define    EXTRF    1
#define    PORF     0

/* MCU Control Register - MCUCR */
#define    SRE      7
#define    SRW10    6
#define    SE       5
#define    SM1      4
#define    SM0      3
#define    SM2      2
#define    IVSEL    1
#define    IVCE     0

/* Timer/Counter Interrupt Flag Register - TIFR */
#define    OCF2     7
#define    TOV2     6
#define    ICF1     5
#define    OCF1A    4
#define    OCF1B    3
#define    TOV1     2
#define    OCF0     1
#define    TOV0     0

/* Timer/Counter Interrupt Mask Register - TIMSK */
#define    OCIE2    7
#define    TOIE2    6
#define    TICIE1   5
#define    OCIE1A   4
#define    OCIE1B   3
#define    TOIE1    2
#define    OCIE0    1
#define    TOIE0    0

/* External Interrupt Flag Register - EIFR */
#define    INTF7    7
#define    INTF6    6
#define    INTF5    5
#define    INTF4    4
#define    INTF3    3
#define    INTF2    2
#define    INTF1    1
#define    INTF0    0

/* External Interrupt Mask Register - EIMSK */
#define    INT7     7
#define    INT6     6
#define    INT5     5
#define    INT4     4
#define    INT3     3
#define    INT2     2
#define    INT1     1
#define    INT0     0

/* External Interrupt Control Register B - EICRB */
#define    ISC71    7
#define    ISC70    6
#define    ISC61    5
#define    ISC60    4
#define    ISC51    3
#define    ISC50    2
#define    ISC41    1
#define    ISC40    0

/* XTAL Divide Control Register - XDIV */
#define    XDIVEN   7
#define    XDIV6    6
#define    XDIV5    5
#define    XDIV4    4
#define    XDIV3    3
#define    XDIV2    2
#define    XDIV1    1
#define    XDIV0    0

/* Stack Pointer Low - SP */
#define    SP7      7
#define    SP6      6
#define    SP5      5
#define    SP4      4
#define    SP3      3
#define    SP2      2
#define    SP1      1
#define    SP0      0

/* Stack Pointer High - SP */
#define    SP15     7
#define    SP14     6
#define    SP13     5
#define    SP12     4
#define    SP11     3
#define    SP10     2
#define    SP9      1
#define    SP8      0

/* Port F Data Direction Register - DDRF */
#define    DDF7     7
#define    DDF6     6
#define    DDF5     5
#define    DDF4     4
#define    DDF3     3
#define    DDF2     2
#define    DDF1     1
#define    DDF0     0
 
/* Port F Data Register - PORTF */
#define    PF7      7
#define    PF6      6
#define    PF5      5
#define    PF4      4
#define    PF3      3
#define    PF2      2
#define    PF1      1
#define    PF0      0
 
/* Port F Data Register - PORTF */
#define    PORTF7   7
#define    PORTF6   6
#define    PORTF5   5
#define    PORTF4   4
#define    PORTF3   3
#define    PORTF2   2
#define    PORTF1   1
#define    PORTF0   0
 
/* Port G Input Pins Address - PING */
#define    PING4    4
#define    PING3    3
#define    PING2    2
#define    PING1    1
#define    PING0    0

/* Port G Data Direction Register - DDRG */
#define    DDG4     4
#define    DDG3     3
#define    DDG2     2
#define    DDG1     1
#define    DDG0     0

/* Port G Data Register - PORTG */
#define    PG4      4
#define    PG3      3
#define    PG2      2
#define    PG1      1
#define    PG0      0

/* Port G Data Register - PORTG */
#define    PORTG4   4
#define    PORTG3   3
#define    PORTG2   2
#define    PORTG1   1
#define    PORTG0   0

/* Store Program Memory Control Register - SPMCR */
#define    SPMIE    7
#define    RWWSB    6
#define    RWWSRE   4
#define    BLBSET   3
#define    PGWRT    2
#define    PGERS    1
#define    SPMEN    0

/* External Interrupt Control Register A - EICRA */
#define    ISC31    7
#define    ISC30    6
#define    ISC21    5
#define    ISC20    4
#define    ISC11    3
#define    ISC10    2
#define    ISC01    1
#define    ISC00    0

/* External Memory Control Register B - XMCRB */
#define    XMBK     7
#define    XMM2     2
#define    XMM1     1
#define    XMM0     0

/* External Memory Control Register A - XMCRA */
#define    SRL2     6
#define    SRL1     5
#define    SRL0     4
#define    SRW01    3
#define    SRW00    2
#define    SRW11    1

/* TWI Status Register - TWSR */
#define    TWS7     7
#define    TWS6     6
#define    TWS5     5
#define    TWS4     4
#define    TWS3     3
#define    TWPS1    1
#define    TWPS0    0

/* TWI Address Register - TWAR */
#define    TWA6     7
#define    TWA5     6
#define    TWA4     5
#define    TWA3     4
#define    TWA2     3
#define    TWA1     2
#define    TWA0     1
#define    TWGCE    0

/* TWI Control Register - TWCR */
#define    TWINT    7
#define    TWEA     6
#define    TWSTA    5
#define    TWSTO    4
#define    TWWC     3
#define    TWEN     2
#define    TWIE     0

/* Timer/Counter1 Control Register C - TCCR1C */
#define    FOC1A    7
#define    FOC1B    6
#define    FOC1C    5

/* Extended Timer/Counter Interrupt Flag Register - ETIFR */
#define    ICF3     5
#define    OCF3A    4
#define    OCF3B    3
#define    TOV3     2
#define    OCF3C    1
#define    OCF1C    0

/* Extended Timer/Counter Interrupt Mask Register - ETIMSK */
#define    TICIE3   5
#define    OCIE3A   4
#define    OCIE3B   3
#define    TOIE3    2
#define    OCIE3C   1
#define    OCIE1C   0

/* Timer/Counter3 Control Register B - TCCR3B */
#define    ICNC3    7
#define    ICES3    6
#define    WGM33    4
#define    WGM32    3
#define    CS32     2
#define    CS31     1
#define    CS30     0

/* Timer/Counter3 Control Register A - TCCR3A */
#define    COM3A1   7
#define    COM3A0   6
#define    COM3B1   5
#define    COM3B0   4
#define    COM3C1   3
#define    COM3C0   2
#define    WGM31    1
#define    WGM30    0

/* Timer/Counter3 Control Register C - TCCR3C */
#define    FOC3A    7
#define    FOC3B    6
#define    FOC3C    5

/* ADC Control and Status Register B - ADCSRB */
#define    ADTS2    2
#define    ADTS1    1
#define    ADTS0    0

/* USART0 Control and Status Register C - UCSR0C */
#define    UMSEL0   6
#define    UPM01    5
#define    UPM00    4
#define    USBS0    3
#define    UCSZ01   2
#define    UCSZ00   1
#define    UCPOL0   0

/* USART1 Control and Status Register B - UCSR1B */
#define    RXCIE1   7
#define    TXCIE1   6
#define    UDRIE1   5
#define    RXEN1    4
#define    TXEN1    3
#define    UCSZ12   2
#define    RXB81    1
#define    TXB81    0

/* USART1 Control and Status Register A - UCSR1A */
#define    RXC1     7
#define    TXC1     6
#define    UDRE1    5
#define    FE1      4
#define    DOR1     3
#define    UPE1     2
#define    U2X1     1
#define    MPCM1    0

/* USART1 Control and Status Register C - UCSR1C */
#define    UMSEL1   6
#define    UPM11    5
#define    UPM10    4
#define    USBS1    3
#define    UCSZ11   2
#define    UCSZ10   1
#define    UCPOL1   0