dm9kend.h

AT91RM9200 BSP with dual ethernet port

#ifndef __dm9kEndh
#define __dm9kEndh

#ifdef __cplusplus
extern "C" {
#endif

#ifndef _ASMLANGUAGE

#include "end.h"
#include "cacheLib.h"
#include "netinet/if_ether.h"
#include "miiLib.h"

/* board level/bus specific and architecture specific macros */

/*=========================================================*/
/* Board/System/Debug information/definition ---------------- */
#define DM9KS_BASE_ADDRESS 0x50000000
#define DM9KS_ADDR_PORT (DM9KS_BASE_ADDRESS+0x300)
#define DM9KS_DATA_PORT (DM9KS_BASE_ADDRESS+0x304)
#define DM9KS_ID		0x90000A46
/*-------register name-----------------------*/
#define DM9KS_NCR		0x00	/* Network control Reg.*/
#define DM9KS_NSR		0x01	/* Network Status Reg.*/
#define DM9KS_TCR		0x02	/* TX control Reg.*/
#define DM9KS_RXCR		0x05	/* RX control Reg.*/
#define DM9KS_BPTR		0x08
#define DM9KS_EPCR		0x0b
#define DM9KS_EPAR		0x0c
#define DM9KS_EPDRL		0x0d
#define DM9KS_EPDRH		0x0e
#define DM9KS_PAR0		0x10	/* Physical Address Register 0 */
#define DM9KS_MAR0		0x16    /* MultiCast Address Register */
#define DM9KS_GPCR		0x1e	/* General purpose control register */
#define DM9KS_GPR		0x1f	/* General purpose register */
#define DM9KS_TCR2		0x2d
#define DM9KS_OTCR              0x2e	
#define DM9KS_SMCR		0x2f 	/* Special Mode Control Reg.*/
#define DM9KS_ETXCSR		0x30	/* Early Transmit control/status Reg.*/
#define	DM9KS_TCCR		0x31	/* Checksum cntrol Reg. */
#define DM9KS_RCSR		0x32	/* Receive Checksum status Reg.*/
#define DM9KS_MRCMDX		0xf0
#define DM9KS_MRCMD		0xf2
#define DM9KS_MDRAL		0xf4
#define DM9KS_MDRAH		0xf5
#define DM9KS_MWCMDX    0xf6
#define DM9KS_MWCMD		0xf8
#define DM9K_MDWAL  0xFA
#define DM9K_MDWAH  0xFB

#define DM9KS_TXPLL		0xfc
#define DM9KS_TXPLH		0xfd
#define DM9KS_ISR		0xfe
#define DM9KS_IMR		0xff
/*---------------------------------------------*/
#define DM9KS_REG05		0x30	/* SKIP_CRC/SKIP_LONG */ 
#define DM9KS_REGFF		0xA3	/* IMR */
#define DM9KS_DISINTR		0x80

#define DM9KS_PHY		0x40	/* PHY address 0x01 */
#define DM9KS_PKT_RDY		0x01	/* Packet ready to receive */

#define DM9KS_VID_L		0x28
#define DM9KS_VID_H		0x29
#define DM9KS_PID_L		0x2A
#define DM9KS_PID_H		0x2B

#define DM9KS_CHIPR		0x2C

#define DM9KS_RX_INTR		0x01
#define DM9KS_TX_INTR		0x02
#define DM9KS_LINK_INTR		0x20
/*------------------------------------------------*/
/* define I/O output and input */
#define OUT_BYTE(addr,data)	(*((volatile UINT8  *) (addr)) = ((UINT8)  (data)))
#define OUT_WORD(addr,data)   (*((volatile UINT16 *) (addr)) = ((UINT16) (data)))
#define OUT_LONG(addr,data)   (*((volatile UINT32 *) (addr)) = ((UINT32) (data)))
#define IN_BYTE(addr)         (*((volatile UINT8  *) (addr)))
#define IN_WORD(addr)         (*((volatile UINT16 *) (addr)))
#define IN_LONG(addr)         (*((volatile UINT32 *) (addr)))
/*=========================================================*/

#define DM9K_IRQ    0x1B       /* dm9000a irq2 */

#define SWAP16(x)	(((x & 0xff) << 8) | (x >> 8))
/* 
 * WARNING -- 
 *   logic in the source code depends on the following being a power of 2 
 */
#define DM9K_N_TX_BUF			256	/* # of transmit buffers */
#define DM9K_N_RX_BUF			256	/* # of receive buffers */
#define DM9K_MAX_SEND_BUF		3072

typedef volatile unsigned char DM9K_REG;    /* DM9000 Register definition */



/* CRC for logical address filter */

#define DM9K_CRC_POLYNOMIAL	0xedb88320	/* CRC polynomial */
#define DM9K_CRC_TO_LAF_IX(crc)	((crc) >> 26)	/* get 6 MSBits */
#define DM9K_LAF_LEN		8    		/* logical addr filter legth */
#define DM9K_LA_LEN		    6		    /* logical address length */
#define MAC_ADDRS_SIZE 		6

/* Special MII flag bit definitions, not the user flag bits */

#define DM9K_USR_MII_BUS_MON     0x01000000      /* monitor the MII bus */
#define DM9K_USR_MII_AN_TBL      0x04000000      /* use auto-negotiation table */
#define DM9K_USR_MII_NO_AN       0x08000000      /* do not auto-negotiate */
#define DM9K_USR_MII_FD          0x10000000      /* allow full duplex */
#define DM9K_USR_MII_100MB       0x20000000      /* allow 100 MB */
#define DM9K_USR_MII_HD          0x40000000      /* allow half duplex */
#define DM9K_USR_MII_10MB        0x80000000      /* allow 10 MB */


/* Definitions for the drvCtrl specific flags field */

#define DM9K_PROMISCUOUS_FLAG     0x1	    /* set the promiscuous mode */
#define DM9K_MEM_ALLOC_FLAG       0x2	    /* allocating memory flag */
#define DM9K_PAD_USED_FLAG        0x4	    /* padding used flag */
#define DM9K_RCV_HANDLING_FLAG    0x8	    /* handling recv packet */
#define DM9K_START_OUTPUT_FLAG    0x10    /* trigger output flag */
#define DM9K_POLLING              0x20    /* polling flag */
#define DM9K_MODE_MEM_IO_MAP	    0x100   /* device registers memory mapped */
#define DM9K_MODE_DWIO	    0x200   /* device in 32 bit mode */

/* The definition of the driver control structure */

typedef struct dm9kDevice
    {
    END_OBJ	endObj;			/* The class we inherit from */
    int 	unit;			/* unit number of the device */
    UINT32  flags;               	/* Our local flags */
    UINT8	enetAddr[6];		/* ethernet address */

    int         ivec;                   /* interrupt vector */
    int         ilevel;                 /* interrupt level */
    UINT32      devAdrs;                /* device structure address */
   

    char *	    pRxMem[DM9K_N_RX_BUF]; /* Base of receive buffers */
    char *	    pTxMem[DM9K_N_TX_BUF]; /* Base of transmit buffers */

    char *      pRxMemBase;             /* Base address of receive buffers */
    char *      pTxMemBase;             /* Base address of transmit buffers */

    int         offset;			/* offset of data in the buffer */

    int         rmdIndex;               /* current RMD index */
    int         rringSize;              /* RMD ring size */

    int         tmdIndex;               /* current TMD index */
    int         tmdLastIndex;           /* last TMD index */
    int         tringSize;              /* TMD ring size */

//    PHY_INFO   *pPhyInfo;		/* info on a MII-compliant PHY */
//    UINT32		miiPhyFlags;	     /* MII-compliant PHY flags */
//    UINT8		phyAddr;	     /* MII-compliant PHY address */
//    MII_AN_ORDER_TBL *	pMiiPhyTbl;	     /* MII-compliant PHY's table */

    CACHE_FUNCS cacheFuncs;             /* cache function pointers */
    BOOL        txBlocked;              /* transmit flow control */
    BOOL        txCleaning;		/* transmit descriptor cleaning */
    CL_POOL_ID  pClPoolId;		/* cluster pool Id */
    M_CL_CONFIG	mClCfg;			/* mBlk & cluster config structure */
    CL_DESC	clDesc;			/* cluster descriptor table */
    END_ERR     lastError;              /* Last error passed to muxError */
    BOOL        errorHandling;          /* task level error handling */
    u_short     errorStat;              /* error status */

	/* added by HL */
	UINT8		io_mode;                /* 0:word, 2:byte ---DM9000A I/O mode */
	UINT8		op_mode;                /* PHY operation mode */
	UINT8 		Speed;			/* current speed */
    } DM9K_DRV_CTRL;


// DM9K_DRV_CTRL * 	dbgDrvCtrl[2];

typedef struct _dm9kS_TdDescriptor {
	unsigned int addr;
	unsigned int size;
}dm9kS_TdDescriptor, *dm9kPS_TdDescriptor;


/* Configuration items */

#define BUS_LATENCY_COUNT	0x1000	/* Max BUS timeo len in 0.1 uSeconds */
#define DM9K_MIN_FBUF		100	/* Minsize of first buffer in chain */
#define DM9K_BUFSIZ		(ETHERMTU + SIZEOF_ETHERHEADER + 6)
#define DM9K_DMA_BUFSIZ	 1536	
#define DM9K_SPEED		1000000
#define DM9K_DEV_NAME		"dm"	/* name of the device */
#define DM9K_DEV_NAME_LEN	3	/* length of the name string */
#define DM9K_APROM_SIZE	32	/* hardware address prom size */

typedef struct _RX_DESC
{
	UINT8 rxbyte;
	UINT8 status;
	UINT16 length;
} RX_DESCR;

typedef union{
	UINT8 buf[4];
	RX_DESCR desc;
} rx_t;


LOCAL int 	dm9kReset (DM9K_DRV_CTRL * pDrvCtrl);
void  		dm9kInt (DM9K_DRV_CTRL * 	pDrvCtrl);
LOCAL STATUS 	dm9kRecv (DM9K_DRV_CTRL * pDrvCtrl);
LOCAL void 	dm9kRestart (DM9K_DRV_CTRL * pDrvCtrl);
LOCAL STATUS 	dm9kRestartSetup (DM9K_DRV_CTRL * pDrvCtrl);
LOCAL void 	dm9kAddrFilterSet (DM9K_DRV_CTRL * pDrvCtrl);
LOCAL void	dm9kConfig (DM9K_DRV_CTRL * pDrvCtrl);
LOCAL STATUS 	dm9kMemInit (DM9K_DRV_CTRL * pDrvCtrl);


LOCAL STATUS     dm9kGetLinkSpeed ( DM9K_DRV_CTRL * pDrvCtrl );

LOCAL void      dm9kEnetAddrGet( DM9K_DRV_CTRL* pDrvCtrl , UINT8* pAddr );


/* END Specific interfaces. */

LOCAL STATUS    dm9kStart (DM9K_DRV_CTRL * pDrvCtrl);
LOCAL STATUS    dm9kStop (DM9K_DRV_CTRL * pDrvCtrl);
LOCAL STATUS    dm9kUnload (DM9K_DRV_CTRL * pDrvCtrl);
LOCAL int       dm9kIoctl (DM9K_DRV_CTRL * pDrvCtrl, int cmd, caddr_t data);
LOCAL STATUS    dm9kSend (DM9K_DRV_CTRL * pDrvCtrl, M_BLK_ID pBuf);
LOCAL STATUS    dm9kMCastAddrAdd (DM9K_DRV_CTRL* pDrvCtrl, char * pAddress);
LOCAL STATUS    dm9kMCastAddrDel (DM9K_DRV_CTRL * pDrvCtrl,
                                   char * pAddress);
LOCAL STATUS    dm9kMCastAddrGet (DM9K_DRV_CTRL * pDrvCtrl,
                                    MULTI_TABLE * pTable);
LOCAL STATUS    dm9kPollSend (DM9K_DRV_CTRL * pDrvCtrl, M_BLK_ID pBuf);
LOCAL STATUS    dm9kPollReceive (DM9K_DRV_CTRL * pDrvCtrl, M_BLK_ID pBuf);
LOCAL STATUS    dm9kPollStart (DM9K_DRV_CTRL * pDrvCtrl);
LOCAL STATUS    dm9kPollStop (DM9K_DRV_CTRL * pDrvCtrl);


//void dm9kIntEnable(void);



IMPORT END_OBJ * dm9kEndLoad (char * initString,void * unused);
IMPORT STATUS 	 dm9kInitParse (DM9K_DRV_CTRL * pDrvCtrl,
				  char * initString);

#endif  /* _ASMLANGUAGE */

#ifdef __cplusplus
}
#endif
/*------------------------------------------*/
static UINT8 regReadByte(UINT8 reg);
static void regWriteByte(UINT8 reg, UINT8 data);
static void writeWord(UINT16 data);
static UINT16 readWord(void);


static UINT16 phy_read(int reg);
static void phy_write(UINT8 reg, UINT16 value);
/*------------------------------------------*/


#endif /* __dm9kEndh */