s1d13806.c

AT91RM9200 BSP with dual ethernet port

		0x41,
		0x00,
		0x85,
		S1D_LUFILEN,
		S1D_16BPP,
		0x0320,
		S1D_NOINKCUR,
		0x01,
		0x00,
		0x00,
		0x00,
		0x1F,
		0x3F,
		0x1F,
		S1D_NOINKCUR,
		0x01,
		0x00,
		0x00,
		0x00,
		0x1F,
		0x3F,
		0x1F,
		S1D_LCDLUTRW_CRTLUTW,
		S1D_PSMD,
		S1D_CRTOM
	},*/
	/** TFT_CRT_Conf Definition File Parameters*/
 	{
		0x1FFF,
		0x0000,
		S1D_BUSCLK_SRC,
		( S1D_SRC_DIV1 | S1D_CLKI_SRC ),
		( S1D_SRC_DIV1 | S1D_CLKI_SRC ),
		( S1D_SRC_DIV1 | S1D_CLKI_SRC ),
		S1D_WS_1,
		S1D_RR_3,
		( ( S1D_TC_0_1 << 8 ) | S1D_TC_0_0 ),
		( S1D_PAN_DW_2 | S1D_PAN_CM | S1D_PAN_TL ),
		0x00,
		0x12,
		0x01,
		0x0B,
		0x2C,
		0x0A,
		0x01,
		S1D_16BPP,
		0x00,
		0x0280,
		0x13,
		0x01,
		0x0B,
		0x2B,
		0x09,
		0x01,
		S1D_LUFILEN,
		S1D_16BPP,
		0x0280,
		S1D_NOINKCUR,
		0x01,
		0x00,
		0x00,
		0x00,
		0x1F,
		0x3F,
		0x1F,
		S1D_NOINKCUR,
		0x01,
		0x00,
		0x00,
		0x00,
		0x1F,
		0x3F,
		0x1F,
		S1D_LCDLUTRW_CRTLUTW,
		S1D_PSMD,
		S1D_EISD0M
	}
} ;

/** S1D13806 Display Resolution Descriptor*/
AT91S_S1D13806_DisplayDefDesc	display_def_desc ;

/** S1D13806 Character Definition Descriptor*/
AT91S_S1D13806_CharDefDesc	char_def_desc ;

/** S1D13806 Data Descriptor*/
AT91S_S1D13806_DataDesc	data_desc ;

/** S1D13806 Register Init Content Descriptor*/
AT91S_S1D13806_RegDesc	s1d13806_reg_desc ;

/** S1D13806 Display Descriptor*/
AT91S_S1D13806_DisplayDesc	s1d13806_display_desc ;

/**----------------------------------------------------------------------------*/
/** \fn    AT91F_S1D13806_Init*/
/** \brief Initialization of the Display Controller*/
/**----------------------------------------------------------------------------*/
void AT91F_S1D13806_Init ( AT91PS_S1D13806_Desc	s1d13806_base, int s1d13806_disp_mem_base, unsigned int conf, unsigned int disp_def, unsigned int char_def, unsigned int mck_khz )
{
	int i ;
	unsigned char	*display_mem = (unsigned char *) s1d13806_disp_mem_base ;
	unsigned int	initial_timeout;
	unsigned char byte;
	byte = s1d13806_base->S1D13806_OnChipReg.OCR_DM&0x7;
	
	if (byte == 0x00 || byte == 0x01)
	{
		conf = TFT_Display_Conf;
	}else   conf = CRT_Display_Conf; //CRT_Display_Conf
	/** Descriptors initialisation*/
	display_def_desc.hdw = Display_def_list[disp_def].hdw ;
	display_def_desc.vdw = Display_def_list[disp_def].vdw ;
	char_def_desc.hnbp = Char_def_list[char_def].hnbp ;
	char_def_desc.vnbp = Char_def_list[char_def].vnbp ;
	data_desc.Present_lcd_start_address = 0 ;
	data_desc.Present_crt_start_address = 0 ;
	data_desc.Present_nb_char_on_line = 0 ;
	data_desc.Present_display_mem_ptr = ( char * ) s1d13806_disp_mem_base ;
	s1d13806_reg_desc.ioconf = Display_conf_list[conf].ioconf ;
	s1d13806_reg_desc.iocr = Display_conf_list[conf].iocr ;
	s1d13806_reg_desc.mclk = Display_conf_list[conf].mclk ;
	s1d13806_reg_desc.lcdclk = Display_conf_list[conf].lcdclk ;
	s1d13806_reg_desc.crtpclk = Display_conf_list[conf].crtpclk ;
	s1d13806_reg_desc.mpclk = Display_conf_list[conf].mpclk ;
	s1d13806_reg_desc.nws = Display_conf_list[conf].nws ;
	s1d13806_reg_desc.refc = Display_conf_list[conf].refc ;
	s1d13806_reg_desc.sdram = Display_conf_list[conf].sdram ;
	s1d13806_reg_desc.ptype = Display_conf_list[conf].ptype ;
	s1d13806_reg_desc.mod = Display_conf_list[conf].mod ;
	s1d13806_reg_desc.lcdhndp = Display_conf_list[conf].lcdhndp ;
	s1d13806_reg_desc.tftfpsp = Display_conf_list[conf].tftfpsp ;
	s1d13806_reg_desc.tftfppw = Display_conf_list[conf].tftfppw ;
	s1d13806_reg_desc.lcdvndp = Display_conf_list[conf].lcdvndp ;
	s1d13806_reg_desc.lcdfpsp = Display_conf_list[conf].lcdfpsp ;
	s1d13806_reg_desc.lcdfppw = Display_conf_list[conf].lcdfppw ;
	s1d13806_reg_desc.lcddm = Display_conf_list[conf].lcddm ;
	s1d13806_reg_desc.lcdm = Display_conf_list[conf].lcdm ;
	s1d13806_reg_desc.lcdmao = Display_conf_list[conf].lcdmao ;
	s1d13806_reg_desc.crthndp = Display_conf_list[conf].crthndp ;
	s1d13806_reg_desc.crthsp = Display_conf_list[conf].crthsp ;
	s1d13806_reg_desc.crthpw = Display_conf_list[conf].crthpw ;
	s1d13806_reg_desc.crtvndp = Display_conf_list[conf].crtvndp ;
	s1d13806_reg_desc.crtvsp = Display_conf_list[conf].crtvsp ;
	s1d13806_reg_desc.crtvpw = Display_conf_list[conf].crtvpw ;
	s1d13806_reg_desc.tvoc = Display_conf_list[conf].tvoc ;
	s1d13806_reg_desc.crtdm = Display_conf_list[conf].crtdm ;
	s1d13806_reg_desc.crtmao = Display_conf_list[conf].crtmao ;
	s1d13806_reg_desc.lcdicc = Display_conf_list[conf].lcdicc ;
	s1d13806_reg_desc.lcdicba = Display_conf_list[conf].lcdicba ;
	s1d13806_reg_desc.lcdicb0 = Display_conf_list[conf].lcdicb0 ;
	s1d13806_reg_desc.lcdicg0 = Display_conf_list[conf].lcdicg0 ;
	s1d13806_reg_desc.lcdicr0 = Display_conf_list[conf].lcdicr0 ;
	s1d13806_reg_desc.lcdicb1 = Display_conf_list[conf].lcdicb1 ;
	s1d13806_reg_desc.lcdicg1 = Display_conf_list[conf].lcdicg1 ;
	s1d13806_reg_desc.lcdicr1 = Display_conf_list[conf].lcdicr1 ;
	s1d13806_reg_desc.crticc = Display_conf_list[conf].crticc ;
	s1d13806_reg_desc.crticba = Display_conf_list[conf].crticba ;
	s1d13806_reg_desc.crticb0 = Display_conf_list[conf].crticb0 ;
	s1d13806_reg_desc.crticg0 = Display_conf_list[conf].crticg0 ;
	s1d13806_reg_desc.crticr0 = Display_conf_list[conf].crticr0 ;
	s1d13806_reg_desc.crticb1 = Display_conf_list[conf].crticb1 ;
	s1d13806_reg_desc.crticg1 = Display_conf_list[conf].crticg1 ;
	s1d13806_reg_desc.crticr1 = Display_conf_list[conf].crticr1 ;
	s1d13806_reg_desc.lutm = Display_conf_list[conf].lutm ;
	s1d13806_reg_desc.psc = Display_conf_list[conf].psc ;
	s1d13806_reg_desc.dm = Display_conf_list[conf].dm ;
	s1d13806_display_desc.RegDesc = &s1d13806_reg_desc ;
	s1d13806_display_desc.DisplayDefDesc = &display_def_desc ;
	s1d13806_display_desc.CharDefDesc = &char_def_desc ;
	s1d13806_display_desc.DataDesc = &data_desc ;
	s1d13806_display_desc.s1d13806_base_add = ( int ) s1d13806_base ;
	s1d13806_display_desc.s1d13806_disp_mem_base_add = ( int ) s1d13806_disp_mem_base ;

	/** S1D13806 Initialisation*/
	s1d13806_base->S1D13806_OnChipReg.OCR_MISC = ( char ) S1D_RME ;	/* Enabling access to the controller */
	s1d13806_base->S1D13806_OnChipReg.OCR_DM = ( char ) S1D_NDM ;		/* Disabling the display outputs */
	s1d13806_base->S1D13806_OnChipReg.OCR_IOCONF = ( short ) s1d13806_display_desc.RegDesc->ioconf ;	/* GPIO Initialization */
	s1d13806_base->S1D13806_OnChipReg.OCR_IOCR = ( short ) s1d13806_display_desc.RegDesc->iocr ;	/* GPIO Initialization */

	/** Program the Clock Source selects*/
	s1d13806_base->S1D13806_OnChipReg.OCR_MCLK = ( char ) s1d13806_display_desc.RegDesc->mclk ;	/* Memory Clock Initialization */
	s1d13806_base->S1D13806_OnChipReg.OCR_LCDCLK = ( char ) s1d13806_display_desc.RegDesc->lcdclk ;
	s1d13806_base->S1D13806_OnChipReg.OCR_CRTPCLK = ( char ) s1d13806_display_desc.RegDesc->crtpclk ;
	s1d13806_base->S1D13806_OnChipReg.OCR_MPCLK = ( char ) s1d13806_display_desc.RegDesc->mpclk ;

	s1d13806_base->S1D13806_OnChipReg.OCR_NWS = ( char ) s1d13806_display_desc.RegDesc->nws ;	/* Setup CPU Wait States */

	/** Program 200us temporizing period*/
	initial_timeout = AT91F_GetTickCount();
	while( AT91F_GetTickCount() < initial_timeout + TIMEOUT_OF_200us);

	/** Configure the memory interface*/
	s1d13806_base->S1D13806_OnChipReg.OCR_REFC = ( char ) s1d13806_display_desc.RegDesc->refc ;	/* SDRAM Refresh Counter */
	s1d13806_base->S1D13806_OnChipReg.OCR_SDRAM = ( short ) s1d13806_display_desc.RegDesc->sdram ;/* SDRAM Timing Control */
	s1d13806_base->S1D13806_OnChipReg.OCR_MEM = ( char ) S1D_SDRAM_INIT ;	/* Memory Configuration */

	/** Program the LCD panel type and panel timing registers*/
	s1d13806_base->S1D13806_OnChipReg.OCR_PTYPE = ( char ) s1d13806_display_desc.RegDesc->ptype ;	/* Panel Configuration Register */
	s1d13806_base->S1D13806_OnChipReg.OCR_MOD = ( char ) s1d13806_display_desc.RegDesc->mod ;		/* Mode Rate */
	s1d13806_base->S1D13806_OnChipReg.OCR_LCDHDW = ( char ) ( ( s1d13806_display_desc.DisplayDefDesc->hdw/8 ) - 1 ) ;	/* Horizontal Display Width */
	s1d13806_base->S1D13806_OnChipReg.OCR_LCDHNDP = ( char ) s1d13806_display_desc.RegDesc->lcdhndp ;	/* Horizontal Non-Display Period */
	s1d13806_base->S1D13806_OnChipReg.OCR_TFTFPSP = ( char ) s1d13806_display_desc.RegDesc->tftfpsp ;	/* FPLINE Start Position */
	s1d13806_base->S1D13806_OnChipReg.OCR_TFTFPPW = ( char ) s1d13806_display_desc.RegDesc->tftfppw ;	/* FPLINE Pulse Width */
	s1d13806_base->S1D13806_OnChipReg.OCR_LCDVDH = ( short ) ( s1d13806_display_desc.DisplayDefDesc->vdw - 1 ) ;	/* Vertical Display Height */
	s1d13806_base->S1D13806_OnChipReg.OCR_LCDVNDP = ( char ) s1d13806_display_desc.RegDesc->lcdvndp ;	/* Vertical Non-Display Period */
	s1d13806_base->S1D13806_OnChipReg.OCR_LCDFPSP = ( char ) s1d13806_display_desc.RegDesc->lcdfpsp ;	/* FPFRAME Start Position */
	s1d13806_base->S1D13806_OnChipReg.OCR_LCDFPPW = ( char ) s1d13806_display_desc.RegDesc->lcdfppw ;	/* FPFRAME Pulse Width */

	/** Program the LCD display output format, memory start locations and FIFO values*/
	s1d13806_base->S1D13806_OnChipReg.OCR_LCDDM = ( char ) s1d13806_display_desc.RegDesc->lcddm ;	/* LCD Display Mode */
	s1d13806_base->S1D13806_OnChipReg.OCR_LCDM = ( char ) s1d13806_display_desc.RegDesc->lcdm ;		/* LCD Miscellaneous */

	s1d13806_base->S1D13806_OnChipReg.OCR_LCDDBA_0 = ( char ) 0x00 ;	/* LCD display start address */
	s1d13806_base->S1D13806_OnChipReg.OCR_LCDDBA_1 = ( char ) 0x00 ;	/* LCD display start address */
	s1d13806_base->S1D13806_OnChipReg.OCR_LCDDBA_2 = ( char ) 0x00 ;	/* LCD display start address */

	s1d13806_base->S1D13806_OnChipReg.OCR_LCDMAO = ( short ) s1d13806_display_desc.RegDesc->lcdmao ;	/* LCD memory address offset */