📄 rtl8019.lst
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C51 COMPILER V7.07 RTL8019 01/14/2009 14:46:42 PAGE 1
C51 COMPILER V7.07, COMPILATION OF MODULE RTL8019
OBJECT MODULE PLACED IN .\RTL8019.obj
COMPILER INVOKED BY: D:\KEIL\C51\BIN\C51.EXE ..\Netif\RTL8019.c BROWSE DEBUG OBJECTEXTEND PRINT(.\RTL8019.lst) OBJECT(.\
-RTL8019.obj)
stmt level source
1 /*
2 * Copyright (c) 2003 Electronic Engineering department of NAN KAI university
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 * 3. The name of the author may not be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
19 * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
20 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
21 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
24 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
25 * OF SUCH DAMAGE.
26 *
27 * Author: zlin <wzzlin@eyou.com>
28 *
29 */
30 #include "..\GloblDef\GloblDef.h"
31 #include "..\TCPIP\TCPIPmem.h"
32 #include "..\Netif\RTL8019.h"
33
34 /* to prevent call RTLSendPacket() when RTLSendPackt() is already is called, InSending
35 is used. example when process run in RTLSendPacket() and a interrupt ocurr then call
36 RTLSendPacket again, then the Register would have changed when interrupt return. */
37 static BYTE DT_XDATA InSending;
38
39 static BYTE DT_XDATA StartPageOfPacket;
40 /* receive head information */
41 /*struct RTLReceiveHeader
42 {
43 BYTE ReceiveStatus;
44 BYTE NextPacketStartPage;
45 BYTE PacketSizeLow;
46 BYTE PacketSizeHigh;
47 }Head;for some unknown resean Head must be a gloal value. */
48 static BYTE DT_XDATA Head[4];
49
50 /* last trasmit start page */
51 static BYTE DT_XDATA LastSendStartPage;
52
53 /* read rtl8019 register. port is reg address */
54 /*BYTE ReadReg(WORD port)
C51 COMPILER V7.07 RTL8019 01/14/2009 14:46:42 PAGE 2
55 {
56 return *((BYTE xdata *)port);
57 }*/
58 #define ReadReg(port) (*((BYTE DT_XDATA *)port))
59
60 /* write value to register */
61 /*void WriteReg(WORD port,BYTE value)
62 {
63 *((BYTE xdata *)port) = value;
64 }*/
65 #define WriteReg(port,value) (*((BYTE DT_XDATA *)port) = value)
66
67 /* select which page of register to use*/
68 /* TO DO:set bit 7-6 in CR, CR_TXP must be 0(if 1 the packet is retrasmit) */
69 #define RTLPage(Index) WriteReg(CR,(ReadReg(CR) & 0x3B)|(BYTE)(Index << 6))
70
71 /* reset rtl8019 and init registers, LocalMacAddr is MAC address */
72 void RTLInit(BYTE LocalMACAddr[]) REENTRANT_MUL
73 {
74 1 BYTE temp;
75 1 int i;
76 1
77 1 /* after hardware reset a longdelay is necessary for rtl to self-initial */
78 1 for(i=0; i < RTL_DELAY_AFTER_HARDWARE_RESET; i++);
79 1
80 1 /* reset: write to reset prot */
81 1 temp = ReadReg(RESET_PORT);
82 1 WriteReg(RESET_PORT,temp);
83 1
84 1 /* init RTL registers*/
85 1 WriteReg(CR,(CR_PAGE0 | CR_ABORT_COMPLETE_DMA | CR_STOP_COMMAND)); /* set page0, stop command. command is
- stop after power up. */
86 1
87 1 WriteReg(PSTART_WPAGE0, RECEIVE_START_PAGE); /* Pstart */
88 1 WriteReg(PSTOP_WPAGE0, RECEIVE_STOP_PAGE); /* Pstop */
89 1 WriteReg(BNRY_WPAGE0, RECEIVE_START_PAGE); /* BNRY */
90 1 WriteReg(TPSR_WPAGE0, SEND_START_PAGE0); /* TPSR */
91 1
92 1 WriteReg(RCR_WPAGE0, 0xCE); /* RCR: refer to define of RCR in Rtl8019as.h */
93 1 WriteReg(TCR_WPAGE0, 0xE0); /* TCR: refer to define of TCR in Rtl8019as.h */
94 1 WriteReg(DCR_WPAGE0, 0xC8); /* DCR: refer to define of DCR in Rtl8019as.h */
95 1
96 1 WriteReg(IMR_WPAGE0,0); /* RTL recieve interrupt enabled */
97 1 WriteReg(ISR_WPAGE0, 0xFF); /* write FF to clear up all interrupt status */
98 1
99 1 RTLPage(1);
100 1
101 1 WriteReg(CURR_WPAGE1,RECEIVE_START_PAGE + 1);
102 1
103 1 /* MAR0 */
104 1 /*WriteReg(0x08,0x00);
105 1 WriteReg(0x09,0x41);
106 1 WriteReg(0x0a,0x00);
107 1 WriteReg(0x0b,0x80);
108 1 WriteReg(0x0c,0x00);
109 1 WriteReg(0x0d,0x00);
110 1 WriteReg(0x0e,0x00);
111 1 WriteReg(0x0f,0x00);*/
112 1
113 1 /* set phisical address */
114 1 WriteReg(PRA0_WPAGE1,LocalMACAddr[0]);
115 1 WriteReg(PRA1_WPAGE1,LocalMACAddr[1]);
C51 COMPILER V7.07 RTL8019 01/14/2009 14:46:42 PAGE 3
116 1 WriteReg(PRA2_WPAGE1,LocalMACAddr[2]);
117 1 WriteReg(PRA3_WPAGE1,LocalMACAddr[3]);
118 1 WriteReg(PRA4_WPAGE1,LocalMACAddr[4]);
119 1 WriteReg(PRA5_WPAGE1,LocalMACAddr[5]);
120 1
121 1 /* transimit start page */
122 1 LastSendStartPage = SEND_START_PAGE0;
123 1 StartPageOfPacket = RECEIVE_START_PAGE + 1;
124 1
125 1 /* in the beginning, no packet is in sending */
126 1 InSending = FALSE;
127 1
128 1 /* initial over, start command and receive */
129 1 WriteReg(CR,(CR_PAGE0 | CR_ABORT_COMPLETE_DMA | CR_START_COMMAND));
130 1 }
131
132 /* write buffer to rlt ram */
133 void RTLWriteRam(WORD address, WORD size, BYTE DT_XDATA * buff) REENTRANT_SIG
134 {
135 1 BYTE DT_XDATA *Endp;
136 1 BYTE PrePage; /* store page */
137 1 PrePage = ReadReg(CR);
138 1 RTLPage(0);
139 1 WriteReg(RSARH_WPAGE0,(BYTE)((address>>8)&0x00ff));
140 1 WriteReg(RSARL_WPAGE0,(BYTE)address);
141 1 WriteReg(RBCRH_WPAGE0,(BYTE)((size>>8)&0x00ff));
142 1 WriteReg(RBCRL_WPAGE0,(BYTE)size);
143 1 WriteReg(CR,(0x00 | CR_REMOTE_WRITE | CR_START_COMMAND));
144 1 for(Endp = buff + size; buff < Endp;)
145 1 {
146 2 WriteReg(REMOTE_DMA_PORT,*(buff++));
147 2 }
148 1 /* complete dma */
149 1 WriteReg(RBCRH_WPAGE0,0);
150 1 WriteReg(RBCRL_WPAGE0,0);
151 1 WriteReg(CR,((PrePage&0xC0) | CR_ABORT_COMPLETE_DMA | CR_START_COMMAND));
152 1 }
153
154 /* read rlt ram data to buffer */
155 void RTLReadRam(WORD address,WORD size,BYTE DT_XDATA * buff) REENTRANT_MUL
156 {
157 1 BYTE DT_XDATA * Endp;
158 1 BYTE PrePage; /* store page */
159 1
160 1 PrePage = ReadReg(CR);
161 1 RTLPage(0);
162 1 WriteReg(RSARH_WPAGE0,(BYTE)((address>>8)&0x00ff));
163 1 WriteReg(RSARL_WPAGE0,(BYTE)address);
164 1 WriteReg(RBCRH_WPAGE0,(BYTE)((size>>8)&0x00ff));
165 1 WriteReg(RBCRL_WPAGE0,(BYTE)size);
166 1 WriteReg(CR,(0x00 | CR_REMOTE_READ | CR_START_COMMAND));
167 1 for(Endp = buff + size; buff < Endp;)
168 1 {
169 2 *(buff++) = ReadReg(REMOTE_DMA_PORT);
170 2 }
171 1 /* complete dma */
172 1 WriteReg(RBCRH_WPAGE0,0);
173 1 WriteReg(RBCRL_WPAGE0,0);
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