📄 aic23rx.asm
字号:
.include "5509regs.inc"
.include "MCBSPregs.inc"
.include "DMAregs.inc"
.mmregs
.ref DelayClock,Delay50ns,Delay1ms
.global AIC23RX,rxdata,txdata,DMA1_ELEMENTNUM
DMA0_ELEMENTNUM .SET 0040H
DMA0_FRAMENUM .SET 0001H
DMA0_ELEMENTNDX .SET 0001H
DMA0_FRAMENDX .SET 0000H
DMA1_ELEMENTNUM .SET 0040H
DMA1_FRAMENUM .SET 0001H
DMA1_ELEMENTNDX .SET 0001H
DMA1_FRAMENDX .SET 0000H
txdata .usect "txdata", 512
rxdata .usect "rxdata", 512
.text
AIC23RX:
MCBSP0_CON:
call Reset_MCBSP1
bset INTM ; Disable ALL INT, INTM = 1
call DelayClock
call MCBSP1_REGWR ;WRITE REG OF MCBSP
;CALL MCBSP0_DMA_CON ;CONFIG DMA USE IN MCBSP
CALL RUN_MCBSP1 ;启动MCBSP
nop
RET
*********************************MCBSP寄存器配置****************************************
MCBSP1_REGWR:
mov #(0b<<15|10b<<13|00b<<11|000b<<8|1b<<7 |0b<<6|00b<<4|0b<<3 |0b<<2|0b<<1| 0b),port(#SPCR1_1)
;SPCR1 ;DLB RJUST CLKSTP Res DXENA Res RINTM RSYNCERR RFULL RRDY RRST
;RESETVALUE ;0 00 00 000 0 0 00 0 0 0 0
mov #(000000b<<10|0b<<9|0b<<8|0b<<7|0b<<6|00b<<4|0b<<3 | 0b<<2 |0b<<1 |0b),port(#SPCR2_1)
;SPCR2 Res FREE SOFT FRST GRST XINTM XSYNCERR XEMPTY XRDY XRST
;resetValue;000000 0 0 0 0 00 0 0 0 0
mov #(0b<<15|0000001b<<8|010b<<5 |00000b),port(#RCR1_1)
;RCR1 Reserved RFRLEN1 RWDLEN1 Reserved
;resetValue;0 0000000 000 00000
mov #(0b<<15|0000000b<<8|000b<<5 |00b<<3 |0b<<2 |01b),port(#RCR2_1)
;RCR2 RPHASE RFRLEN2 RWDLEN2 RCOMPAND RFIG RDATDLY
;resetValue;0 0000000 000 00 0 00
mov #(0b<<15|0000001b<<8|010b<<5 |00000b),port(#XCR1_1)
;XCR1 Reserved XFRLEN1 XWDLEN1 Reserved
;resetValue;0 0000000 000 00000
mov #(0b<<15|0000000b<<8|000b<<5 |00b<<3 |0b<<2 |01b),port(#XCR2_1)
;XCR2 XPHASE XFRLEN2 XWDLEN2 XCOMPAND XFIG XDATDLY
;resetValue;0 0000000 000 00 0 00
; mov #(00000000b<<8|00000000b),port(#SRGR1_0)
;SRGR1 FWIDR CLKGDV
;resetValue;000000000 0000000010
;mov #(0b<<15|0b<<14|1b<<13| 0b<<12|000000000000b),port(#SRGR2_0)
;SRGR2 GSYNC CLKSP CLKSM FSGM FPER
;resetValue;0 0 1 0 000000000000
mov #(0b<<15|0b<<14|0b<<13|0b<<12|0b<<11|0b<<10|0b<<9|0b<<8 |0b<<7| 0b<<6 | 0b<<5|0b<<4 |0b<<3|1b<<2 |1b<<1 |1b),port(#PCR1)
;PCR Reserved IDLEEN XIOEN RIOEN FSXM FSRM CLKXM CLKRM SCLKME CLKSSTAT DXSTAT DRSTAT FSXP FSRP CLKXP CLKRP
;resetValue;000000000000000000
RET
**********************************************************************************************8888
********************DMA FOR MCBSP
MCBSP0_DMA_CON:
mov #(0000000000000b<<4|1b<<3|0b<<2 | 0b<<1 |0b),port(#DMA_GCR)
;DMA_GCR Reserved Res. FREE EHPIEXCL EHPIPRIO
;resetValue;0000000000000 1 0 0 0
;DMA Channel 0 Control Register 0000 0000 0000 0000
mov #(00b<<14|01b<<12 |1b<<11 |0b<<10 |1b<<9 |1b<<8 |0b<<7 |0b<<6|0b<<5|00010b),port(#DMA_CCR0)
;DMA_CCR: DSTAMODE SRCAMODE ENDPROG Reserve REPEAT AUTOINIT EN PRIO FS SYNC
;RESETVALUE 0000000000000000000
;DMA Channel 0 Interrupt Control Register xxxx xxxx xx00 0011
mov #(0000000000b<<6 |1b<<5 |0b<<4 |0b<<3 |1b<<2 |0b<<1 |0b),port(#DMA_CICR0)
;DMA_CICR: Reserved BLOCKIE LASTIE FRAMEIE HALFIE DROPIE TIMEOUTIE
; 1 1
;DMACSR;DMA Channel 0 Status Register xxxx xxxx xx00 0000
; mov #(0000000000b<<7 |0b<<6 |0b<<5 |0b<<4 |0b<<3|0b<<2 |0b<<1 |0b),port(#DMA_CSR0)
; Reserved SYNC BLOCK LAST FRAME HALF DROP TIMEOUT
;00000000
mov port(#DMA_CSR0),T1
;用来读的
;DMA_CSDP ;DMA Channel 0 Source Destination Parameters Register 0000 0000 0000 0000
mov #(00b<<14|0b<<13 |0011b<<9|00b<<7 |0b<<6 |0001b<<2 |01b),port(#DMA_CSDP0)
; DSTBEN DSTPACK DST SRCBEN SRCPACK SRC DATATYPE
ld #rxdata,#1,AC3 ;回放RAM存储区
mov AC3,port(#DMA_CSSA_L0) ;源地址DMA Channel 0 Source Start Address Register lower
mov #0000H,port(#DMA_CSSA_U0) ;DMA Channel 0 Source Start Address Register uper
mov #05006H,port(#DMA_CDSA_L0) ;目的地址DMA Channel 0 Destination Start Address Register(lower bits)
mov #0000H,port(#DMA_CDSA_U0) ;DMA Channel 0 Destination Start Address Register(upper bits)
mov #DMA0_ELEMENTNUM,port(#DMA_CEN0) ;DMA Channel 0 Element Number Register Undefined
mov #DMA0_FRAMENUM,port(#DMA_CFN0) ;DMA Channel 0 Frame Number Register Undefined
mov #DMA0_ELEMENTNDX,port(#DMA_CFI0) ;DMA Channel 0 Frame Index Register Undefined
mov #DMA0_FRAMENDX,port(#DMA_CEI0) ;DMA Channel 0 Element Index Register Undefined
mov #(01b<<14|00b<<12 |1b<<11 |0b<<10 |1b<<9 |1b<<8 |0b<<7 |0b<<6|0b<<5|00001b),port(#DMA_CCR1)
;DMA_CCR: DSTAMODE SRCAMODE ENDPROG Reserve REPEAT AUTOINIT EN PRIO FS SYNC
;RESETVALUE 0000000000000000000
;DMA Channel 0 Interrupt Control Register xxxx xxxx xx00 0011
mov #(0000000000b<<6 |1b<<5 |0b<<4 |0b<<3 |1b<<2 |0b<<1 |0b),port(#DMA_CICR1)
;DMA_CICR: Reserved BLOCKIE LASTIE FRAMEIE HALFIE DROPIE TIMEOUTIE
mov port(#DMA_CSR1),T1
;DMA_CSDP ;DMA Channel 0 Source Destination Parameters Register 0000 0000 0000 0000
mov #(00b<<14|0b<<13 |0001b<<9|00b<<7 |0b<<6 |0011b<<2 |01b),port(#DMA_CSDP1)
; DSTBEN DSTPACK DST SRCBEN SRCPACK SRC DATATYPE
mov #05002h,port(#DMA_CSSA_L1) ;DMA端口地址 Channel 0 Source Start Address Register lower
mov #0000H,port(#DMA_CSSA_U1) ;DMA Channel 0 Source Start Address Register uper
ld #rxdata,#1,AC3 ;接收存储RAM地址
mov AC3,port(#DMA_CDSA_L1) ;DMA Channel 0 Destination Start Address Register(lower bits)
mov #0000H,port(#DMA_CDSA_U1) ;DMA Channel 0 Destination Start Address Register(upper bits)
mov #DMA1_ELEMENTNUM,port(#DMA_CEN1) ;DMA Channel 0 Element Number Register Undefined
mov #DMA1_FRAMENUM,port(#DMA_CFN1) ;DMA Channel 0 Frame Number Register Undefined
mov #DMA1_ELEMENTNDX,port(#DMA_CFI1) ;DMA Channel 0 Frame Index Register Undefined
mov #DMA1_FRAMENDX,port(#DMA_CEI1) ;DMA Channel 0 Element Index Register Undefined
ORM #(1b<<7),port(#DMA_CCR0) ;DMA音频回放 ENABLE
call DelayClock
ORM #(1b<<7),port(#DMA_CCR1) ; DMA音频接收 ENABLE
RET
*******
Reset_MCBSP1:
ANDM #1111111111111110B,port(#SPCR1_1) ; Reset RRST
call DelayClock
ANDM #1111111110011110B,port(#SPCR2_1) ;FRST GRST XRST
call DelayClock
ANDM #(00b<<6|0b),port(#SPCR2_1) ;7 6 0
ret
***********
RUN_MCBSP1:
ORM #(1b<<6),port(#SPCR2_1); PULL SAMPLE RATE GENERATOR OUT OF RESET
call DelayClock
ORM #(1b),port(#SPCR1_1) ; PULL RX OUT OF RESET
ORM #(1b),port(#SPCR2_1) ; PULL TX OUT OF RESET, XRDY WILL TRANSIT FROM 0->1
ORM #(1b<<7),port(#SPCR2_1); PULL FRAME SYNC GENERATOR OUT OF RESET
call DelayClock
ret
***************************************
DMA3CONFIG:
mov #(00b<<14|01b<<12 |1b<<11 |0b<<10 |1b<<9 |1b<<8 |0b<<7 |0b<<6|0b<<5|00010b),port(#DMA_CCR3)
;DMA_CCR: DSTAMODE SRCAMODE ENDPROG Reserve REPEAT AUTOINIT EN PRIO FS SYNC
;RESETVALUE 0000000000000000000
;DMA Channel 0 Interrupt Control Register xxxx xxxx xx00 0011
mov #(0000000000b<<6 |1b<<5 |0b<<4 |1b<<3 |0b<<2 |0b<<1 |0b),port(#DMA_CICR3)
;DMA_CICR: Reserved BLOCKIE LASTIE FRAMEIE HALFIE DROPIE TIMEOUTIE
; 1 1
;DMACSR;DMA Channel 0 Status Register xxxx xxxx xx00 0000
; mov #(0000000000b<<7 |0b<<6 |0b<<5 |0b<<4 |0b<<3|0b<<2 |0b<<1 |0b),port(#DMA_CSR0)
; Reserved SYNC BLOCK LAST FRAME HALF DROP TIMEOUT
;00000000
mov port(#DMA_CSR3),T1
;用来读的
;DMA_CSDP ;DMA Channel 0 Source Destination Parameters Register 0000 0000 0000 0000
mov #(00b<<14|0b<<13 |0011b<<9|00b<<7 |0b<<6 |0001b<<2 |01b),port(#DMA_CSDP3)
; DSTBEN DSTPACK DST SRCBEN SRCPACK SRC DATATYPE
ld #rxdata,#1,AC3
mov AC3,port(#DMA_CSSA_L3) ;DMA Channel 0 Source Start Address Register lower
mov #0000H,port(#DMA_CSSA_U3) ;DMA Channel 0 Source Start Address Register uper
mov #05006H,port(#DMA_CDSA_L3) ;DMA Channel 0 Destination Start Address Register(lower bits)
mov #0000H,port(#DMA_CDSA_U3) ;DMA Channel 0 Destination Start Address Register(upper bits)
mov #DMA0_ELEMENTNUM,port(#DMA_CEN3) ;DMA Channel 0 Element Number Register Undefined
mov #DMA0_FRAMENUM,port(#DMA_CFN3) ;DMA Channel 0 Frame Number Register Undefined
mov #DMA0_ELEMENTNDX,port(#DMA_CFI3) ;DMA Channel 0 Frame Index Register Undefined
mov #DMA0_FRAMENDX,port(#DMA_CEI3) ;DMA Channel 0 Element Index Register Undefined
RET
**Uint16 DATA_PAGE1[4]={ 0x0001,0x0002,0x0003,0x0004 };
**Uint16 DATA_PAGE2[31]=
* { 0x4109,0x0a00,0x0000,0xc580,0x44f0,0x3800,0x4C00,
* 0x6be3,0x6996,0x675d,0x6be3,0x9666,0x675d,0x7d83,0x84ee,0x7d83,0x84ee,
* 0x6be3,0x9666,0x675d,0x6be3,0x9666,0x675d,0x7d83,0x84ee,0x7d83,0x84ee,
* 0x8118,0x1680,0x0000,0xfe90
* };**
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