statemachine.rpt

自动打铃系统的VHDL设计中的状态机

        | | +--------------------------- LC32 AdjBotton2
        | | | +------------------------- LC20 Command0
        | | | | +----------------------- LC19 Command1
        | | | | | +--------------------- LC18 Command2
        | | | | | | +------------------- LC17 Command3
        | | | | | | | +----------------- LC21 Command4
        | | | | | | | | +--------------- LC28 Flash0
        | | | | | | | | | +------------- LC27 Flash1
        | | | | | | | | | | +----------- LC26 Flash2
        | | | | | | | | | | | +--------- LC22 State2
        | | | | | | | | | | | | +------- LC23 State1
        | | | | | | | | | | | | | +----- LC24 State0
        | | | | | | | | | | | | | | +--- LC25 Pos1
        | | | | | | | | | | | | | | | +- LC30 ~1471~1
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC20 -> - - - - - - - - - - - - - - * * | - * | <-- Command0
LC19 -> - - - - - - - - - - - - - - * * | - * | <-- Command1
LC18 -> - - - - - - - - - - - - - - * * | - * | <-- Command2
LC17 -> - - - - - - - - - - - - - - * * | - * | <-- Command3
LC21 -> - - - - - - - - - - - - - - * * | - * | <-- Command4
LC22 -> - - - * * * * * - - - * * * * * | * * | <-- State2
LC23 -> - - - * * * * * - - - * * * * * | * * | <-- State1
LC24 -> - - - * * * * * - - - * * * * * | * * | <-- State0
LC25 -> * * * - - - - - * * * - - - * * | * * | <-- Pos1

Pin
4    -> - - - - - - - - - - - - - - * * | * * | <-- AdjPosition
6    -> * * * - - - - - - - - - - - - - | - * | <-- AdjVal
5    -> - - - - - - - - - - - * * * - - | - * | <-- ChangeMode
43   -> - - - - - - - - - - - - - - - - | - - | <-- Clock
LC4  -> * * * - - - - - * * * - - - * - | * * | <-- Pos0


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                 c:\max2work\vhdl\statemachine.rpt
statemachine

** EQUATIONS **

AdjPosition : INPUT;
AdjVal   : INPUT;
ChangeMode : INPUT;
Clock    : INPUT;

-- Node name is 'AdjBotton0' = ':19' 
-- Equation name is 'AdjBotton0', type is output 
 AdjBotton0 = DFFE( _EQ001 $  GND, GLOBAL( Clock),  VCC,  VCC,  VCC);
  _EQ001 =  AdjVal &  Pos0 &  Pos1;

-- Node name is 'AdjBotton1' = ':17' 
-- Equation name is 'AdjBotton1', type is output 
 AdjBotton1 = DFFE( _EQ002 $  GND, GLOBAL( Clock),  VCC,  VCC,  VCC);
  _EQ002 =  AdjVal & !Pos0 &  Pos1;

-- Node name is 'AdjBotton2' = ':15' 
-- Equation name is 'AdjBotton2', type is output 
 AdjBotton2 = DFFE( _EQ003 $  GND, GLOBAL( Clock),  VCC,  VCC,  VCC);
  _EQ003 =  AdjVal &  Pos0 & !Pos1;

-- Node name is 'Command0' = ':13' 
-- Equation name is 'Command0', type is output 
 Command0 = DFFE( _EQ004 $  GND, GLOBAL( Clock),  VCC,  VCC,  VCC);
  _EQ004 =  State0 & !State1 & !State2;

-- Node name is 'Command1' = ':11' 
-- Equation name is 'Command1', type is output 
 Command1 = DFFE( _EQ005 $  GND, GLOBAL( Clock),  VCC,  VCC,  VCC);
  _EQ005 = !State0 &  State1 & !State2;

-- Node name is 'Command2' = ':9' 
-- Equation name is 'Command2', type is output 
 Command2 = DFFE( _EQ006 $  GND, GLOBAL( Clock),  VCC,  VCC,  VCC);
  _EQ006 =  State0 &  State1 & !State2;

-- Node name is 'Command3' = ':7' 
-- Equation name is 'Command3', type is output 
 Command3 = DFFE( _EQ007 $  GND, GLOBAL( Clock),  VCC,  VCC,  VCC);
  _EQ007 = !State0 & !State1 &  State2;

-- Node name is 'Command4' = ':5' 
-- Equation name is 'Command4', type is output 
 Command4 = DFFE( _EQ008 $  State2, GLOBAL( Clock),  VCC,  VCC,  VCC);
  _EQ008 = !State0 & !State1 &  State2;

-- Node name is 'Flash0' = ':25' 
-- Equation name is 'Flash0', type is output 
 Flash0  = DFFE( _EQ009 $  Pos0, GLOBAL( Clock),  VCC,  VCC,  VCC);
  _EQ009 =  Pos0 & !Pos1;

-- Node name is 'Flash1' = ':23' 
-- Equation name is 'Flash1', type is output 
 Flash1  = DFFE( _EQ010 $  Pos1, GLOBAL( Clock),  VCC,  VCC,  VCC);
  _EQ010 =  Pos0 &  Pos1;

-- Node name is 'Flash2' = ':21' 
-- Equation name is 'Flash2', type is output 
 Flash2  = DFFE( _EQ011 $  Pos0, GLOBAL( Clock),  VCC,  VCC,  VCC);
  _EQ011 =  Pos0 &  Pos1;

-- Node name is ':31' = 'Pos0' 
-- Equation name is 'Pos0', location is LC004, type is buried.
Pos0     = DFFE( _EQ012 $  VCC, GLOBAL( Clock),  VCC,  VCC,  VCC);
  _EQ012 = !_LC030 &  _X001 &  _X002 &  _X003 &  _X004 &  _X005 &  _X006 & 
              _X007;
  _X001  = EXP( Pos0 &  Pos1 &  State1 & !State2);
  _X002  = EXP(!AdjPosition &  Pos0 &  State0 & !State2);
  _X003  = EXP( AdjPosition & !Pos0 &  State0 & !State2);
  _X004  = EXP( Pos0 & !State0 & !State1 &  State2);
  _X005  = EXP( AdjPosition & !Pos0 &  State1 & !State2);
  _X006  = EXP(!AdjPosition &  Pos0 &  State1 & !State2);
  _X007  = EXP( AdjPosition & !State0 & !State1 &  State2);

-- Node name is ':30' = 'Pos1' 
-- Equation name is 'Pos1', location is LC025, type is buried.
Pos1     = DFFE( _EQ013 $  _EQ014, GLOBAL( Clock),  VCC,  VCC,  VCC);
  _EQ013 = !Command0 &  Command1 & !Command2 & !Command3 & !Command4 & 
              State0 &  State1 & !State2 &  _X008 &  _X009 &  _X010 &  _X011 & 
              _X012 &  _X013 &  _X014 &  _X015
         # !Command0 & !Command1 &  Command2 & !Command3 & !Command4 & 
             !State0 & !State1 &  _X008 &  _X009 &  _X010 &  _X011 &  _X012 & 
              _X013 &  _X014 &  _X015
         # !Command0 & !Command1 & !Command2 & !Command3 & !Command4 & 
             !State1 & !State2 &  _X008 &  _X009 &  _X010 &  _X011 &  _X012 & 
              _X013 &  _X014 &  _X015
         # !Command1 & !Command2 & !Command3 & !Command4 & !State0 & !State2 & 
              _X008 &  _X009 &  _X010 &  _X011 &  _X012 &  _X013 &  _X014 & 
              _X015;
  _X008  = EXP( AdjPosition &  Pos0 &  Pos1 & !State2);
  _X009  = EXP(!State0 & !State1 & !State2);
  _X010  = EXP( AdjPosition &  Pos1 &  State1 & !State2);
  _X011  = EXP( AdjPosition &  Pos1 & !State0 & !State1);
  _X012  = EXP(!AdjPosition & !Pos1 & !State0 & !State1);
  _X013  = EXP(!Pos0 & !Pos1 & !State0 & !State1);
  _X014  = EXP(!AdjPosition & !Pos1 & !State2);
  _X015  = EXP(!Pos0 & !Pos1 & !State2);
  _EQ014 =  _X008 &  _X009 &  _X010 &  _X011 &  _X012 &  _X013 &  _X014 & 
              _X015;
  _X008  = EXP( AdjPosition &  Pos0 &  Pos1 & !State2);
  _X009  = EXP(!State0 & !State1 & !State2);
  _X010  = EXP( AdjPosition &  Pos1 &  State1 & !State2);
  _X011  = EXP( AdjPosition &  Pos1 & !State0 & !State1);
  _X012  = EXP(!AdjPosition & !Pos1 & !State0 & !State1);
  _X013  = EXP(!Pos0 & !Pos1 & !State0 & !State1);
  _X014  = EXP(!AdjPosition & !Pos1 & !State2);
  _X015  = EXP(!Pos0 & !Pos1 & !State2);

-- Node name is ':29' = 'State0' 
-- Equation name is 'State0', location is LC024, type is buried.
State0   = DFFE( _EQ015 $  ChangeMode, GLOBAL( Clock),  VCC,  VCC,  VCC);
  _EQ015 =  ChangeMode &  State1 &  State2
         #  State0;

-- Node name is ':28' = 'State1' 
-- Equation name is 'State1', location is LC023, type is buried.
State1   = TFFE( _EQ016, GLOBAL( Clock),  VCC,  VCC,  VCC);
  _EQ016 =  ChangeMode &  State0 & !State1 & !State2
         #  ChangeMode &  State0 &  State1
         #  ChangeMode &  State1 &  State2;

-- Node name is ':27' = 'State2' 
-- Equation name is 'State2', location is LC022, type is buried.
State2   = TFFE( _EQ017, GLOBAL( Clock),  VCC,  VCC,  VCC);
  _EQ017 =  ChangeMode &  State0 &  State1 & !State2
         #  ChangeMode &  State0 & !State1 &  State2
         #  ChangeMode &  State1 &  State2;

-- Node name is '~1471~1' 
-- Equation name is '~1471~1', location is LC030, type is buried.
-- synthesized logic cell 
_LC030   = LCELL( _EQ018 $  GND);
  _EQ018 = !Command0 &  Command1 & !Command2 & !Command3 & !Command4 & 
              State0 &  State1 & !State2
         # !Command0 & !Command1 &  Command2 & !Command3 & !Command4 & 
             !State0 & !State1 &  State2
         # !Command0 & !Command1 & !Command2 & !Command3 & !Command4 & 
              State0 & !State1 & !State2
         # !Command1 & !Command2 & !Command3 & !Command4 & !State0 &  State1 & 
             !State2
         #  AdjPosition &  Pos1 &  State0 & !State2;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                          c:\max2work\vhdl\statemachine.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,683K