readandwrite.vhd

三星k9系列flash memory读写程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity readandwrite is
port(
     ale    : out std_logic;
     cle    : out std_logic;
     we     : out std_logic;
     re     : out std_logic;
     ce     : out std_logic;
     rb     : out std_logic;
     data   : out std_logic_vector(7 downto 0);
     clk    : in std_logic;
     reset  : in std_logic;
     mread  : in std_logic;--read mode
     mwrite : in std_logic;--write mode
     merase : in std_logic;--erase mode
    
     fifod  : in std_logic_vector(7 downto 0)--fifo外部端口数据
     );
End readandwrite;
Architecture behariral of readandwrite is
Signal f_ale : std_logic;
Signal f_cle : std_logic;
Signal f_we  : std_logic;
Signal f_re  : std_logic;
Signal f_ce  : std_logic;
signal flashd : std_logic_vector(7 downto 0);--flash数据输出
Signal f_addra : std_logic_vector(10 downto 0);--fifo写指针
Signal f_addrb : std_logic_vector(10 downto 0);--fifo读指针
Signal f_countbyte : std_logic_vector(11 downto 0);--one page bytes count
Signal f_countp : std_logic_vector(5 downto 0);--one block page count
Signal f_countb : std_logic_vector(12 downto 0);--one flash block count
Signal f_data : std_logic_vector(7 downto 0);--data to the flash io
signal rb_delay : std_logic_vector(3 downto 0);
signal f_rb : std_logic;
Type wr is(
           wr0,wr1,wr2,wr3,wr4,wr5,wr6,wr7,wr8,wr9,Wr10,wr11,wr12,wr13,wr14,wr15,
           wr16,wr17,wr18,wr19,wr20,wr21,wr22,wr23,wr24,wr25,wr26,wr27,wr28
           );
Signal w_state :wr;
type   rd is(
          rd0,rd1,rd2,rd3,rd4,rd5,rd6,rd7,rd8,rd9,
          rd10,rd11,rd12,rd13,rd14,rd15,rd16,rd17,rd18,rd19,rd20,rd21,rd22
          );
signal r_state :rd;
begin
ale<=f_ale;
cle<=f_cle;
we<=f_we;
re<=f_re;
main:process(clk,reset)
begin
if reset='0' then
w_state <=wr0;
f_ale<='0';
f_cle<='0';
f_we<='0';
f_re<='1';
f_addrb<="00000000000";
f_countbyte<="000000000000";
f_countp<="000000";
f_countb<="0000000000000";
rb_delay<="0000";
w_state<=wr0;
r_state<=rd0;
elsif clk'event and clk='1' then
ce<='0';
if mwrite='1'then
 case w_state is
  when wr0=>
   f_cle<='1';
   f_data<="10000000";--write ox08h command
   w_state<=wr1;
  when wr1=>
   f_we<='1';
   w_state<=wr2;
  when wr2=>
   f_we<='1';
   f_cle<='0';
   f_ale<='1';
   w_state<=wr3;
  when wr3=>
   f_we<='0';
   w_state<=wr4;
  when wr4=>
   f_we<='1';
   f_data<=f_countbyte(7 downto 0);
   w_state<=wr5;
  when wr5=>
   f_we<='0';
   w_state<=wr6;
  when wr6=>
   f_we<='1';
   f_data(3 downto 0)<=f_countbyte(11 downto 8);
   w_state<=wr7;
  when wr7=>
   f_we<='0';
   w_state<=wr8;
  when wr8=>
   f_we<='1';
   f_data(5 downto 0)<=f_countp;
   f_data(7 downto 6)<=f_countb(1 downto 0);
   w_state<=wr9;
  when wr9=>
   f_we<='0';
   w_state<=wr10;
  when wr10=>
   f_we<='1';
   f_data<=f_countb(9 downto 2);
   w_state<=wr11;
  when wr11=>
   f_we<='0';
   w_state<=wr12;
  when wr12=>
   f_we<='1';
   f_data(2 downto 0)<=f_countb(12 downto 10);
   w_state<=wr13;
  when wr13=>
   f_ale<='0';
   f_we<='1';
   w_state<=wr14;
  when wr14=>
   f_we<='0';
   f_data<=fifod;
   f_countbyte<= f_countbyte+1;
   if f_countbyte="00000000000"then
   w_state<=wr15;
   else
   w_state<=wr13;
   end if;
  when wr15=>
   f_we<='1';
   w_state<=wr16;
  when wr16=>
   f_cle<='1';
   f_data<="00010000";--写ox10h命令
   w_state<=wr17;
  when wr17=>
   f_we<='0';
   w_state<=wr18;
  when wr18=>
   f_we<='1';
   w_state<=wr19;
  when wr19=>
   rb_delay<=rb_delay+1;
    if rb_delay="1111" then
    w_state<=wr20;
    else 
    w_state<=wr19;
    end if;
  when wr20=> 
   f_we<='0';
   w_state<=wr21;
  when wr21=>
   f_we<='1';
   f_data<="01110000";--ox70h命令
   w_state<=wr22;
  when wr22=>
   f_cle<='0';
   w_state<=wr23;
  when wr23=>
   f_re<='0';
   w_state<=wr24;
  when wr24=>
   f_re<='1';
   f_data<=fifod;
   w_state<=wr25;
  when wr25=>
   if f_data(6)='1' or f_rb='1'then
   w_state<=wr26;
   else
   w_state<=wr25;
   end if;
  when wr26=>
   if f_data(0)='0'then
   f_countp<=f_countp+1;
   w_state<=wr27;
   end if;
  when wr27=>
   if f_countp="111111"then
   f_countb<=f_countb+1;
   w_state<=wr28;
   end if;
  when wr28=>
   if f_countb="1111111111111"then
   w_state<=wr28;
   else
   w_state<=wr0;
   end if;
  when others=>
   w_state<=wr0;
  end case;
elsif mread='1'then
  f_addrb<="00000000000";
  f_countbyte<="000000000000";
  f_countp<="000000";
  f_countb<="0000000000000";
  rb_delay<="0000";
 case r_state is
 when rd0=>
  f_cle<='1';
  r_state<=rd1;
 when rd1=>
  f_we<='1';
  f_data<="00000000";--写ox00h命令
  r_state<=rd2;
 when rd2=>
  f_cle<='0';
  r_state<=rd3;
 when rd3=>
  f_ale<='1';
  r_state<=rd4;
 when rd4=>
  f_we<='0';
  r_state<=rd5;
 when rd5=>
  f_we<='1';
  f_data<=f_countbyte(7 downto 0);
  r_state<=rd6;
 when rd6=>
  f_we<='0';
  r_state<=rd7;
 when rd7=>
  f_we<='1';
  f_data(3 downto 0)<=f_countbyte(11 downto 8);
  r_state<=rd8;
 when rd8=>
  f_we<='0';
  r_state<=rd9;
 when rd9=>
  f_we<='1';
  f_data(5 downto 0)<=f_countp;
  f_data(7 downto 6)<=f_countb(1 downto 0);
  r_state<=rd10;
 when rd10=>
  f_we<='0';
  r_state<=rd11;
 when rd11=>
  f_we<='1';
  f_data<=f_countb(9 downto 2);
  r_state<=rd12;
 when rd12=>
  f_we<='0';
  r_state<=rd13;
 when rd13=>
  f_we<='1';
  f_data(2 downto 0)<=f_countb(12 downto 10);
  r_state<=rd14;
 when rd14=>
  f_ale<='0';
  f_cle<='1';
  r_state<=rd15;
 when rd15=>
  f_we<='0';
  r_state<=rd16;
 when rd16=>
  f_we<='1';
  f_data<="00110000";--写ox30h命令
  r_state<=rd17;
 when rd17=>
  f_cle<='0';
  f_rb<='0';
  rb_delay<=rb_delay-1;
   if rb_delay="0000"then
   r_state<=rd18;
   else 
   r_state<=rd17;
   end if;
 when rd18=>
  f_rb<='1';
  r_state<=rd19;
 when rd19=>
  f_re<='0';
  r_state<=rd20;
 when rd20=>
  f_re<='1';
  r_state<=rd21;
 when rd21=>
  f_re<='0';
  f_data<=flashd;
  data<=f_data;
  f_countbyte<=f_countbyte+1;
  if f_countbyte="11111111111"then
  f_countp<=f_countp+1;
  r_state<=rd22;
  else
  r_state<=rd20;
  end if;
 when rd22=>
  if f_countp="111111"then
  f_countb<=f_countb+1;
  end if;
  r_state<=rd0;
 when others=>
  r_state<=rd0;
  end case;
  end if;
 end if;
end process main;
end behariral;