📄 lcd_pg320240.lst
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016A E00D 650 MOV R13,#00h
016C BB9A 651 CALLR _lcd_set_reg
652 ; lcd_pg320240.c 159
653 ; lcd_pg320240.c 160 /* Register 0Ah - Vertical Non-Display Register Calculated in
conjunction with register 08h (HNDP) to
654 ; lcd_pg320240.c 161 achieve the desired frame rate. */
655 ; lcd_pg320240.c 162 // lcd_set_reg(0x0A, 0x3B);
656 ; lcd_pg320240.c 163 lcd_set_reg(0x0A, 0x26);
657 ?LINE 163
016E E0AC 658 MOV R12,#0Ah
0170 E6FD2600 659 MOV R13,#026h
0174 BB96 660 CALLR _lcd_set_reg
661 ; lcd_pg320240.c 164 lcd_set_reg(0x0B, 0x00); //Register 0Bh - MOD Rate - not
used by this panel
662 ?LINE 164
0176 E0BC 663 MOV R12,#0Bh
0178 E00D 664 MOV R13,#00h
017A BB93 665 CALLR _lcd_set_reg
666 ; lcd_pg320240.c 165 lcd_set_reg(0x0C, 0x00); //Register 0Ch - Screen 1 Start
Word Address LSB
667 ?LINE 165
017C E0CC 668 MOV R12,#0Ch
017E E00D 669 MOV R13,#00h
0180 BB90 670 CALLR _lcd_set_reg
671 ; lcd_pg320240.c 166 lcd_set_reg(0x0D, 0x00); //Register 0Dh - Screen 1 Start
Word Address MS. Start address should be set to 0B
672 ?LINE 166
0182 E0DC 673 MOV R12,#0Dh
0184 E00D 674 MOV R13,#00h
0186 BB8D 675 CALLR _lcd_set_reg
676 ; lcd_pg320240.c 167 lcd_set_reg(0x0F, 0x00); //Register 0Fh - Screen 2 Start
Word Address LSB
677 ?LINE 167
0188 E0FC 678 MOV R12,#0Fh
018A E00D 679 MOV R13,#00h
018C BB8A 680 CALLR _lcd_set_reg
681 ; lcd_pg320240.c 168 lcd_set_reg(0x10, 0x00); //Register 10h - Screen 2 Start
Word Address MSB. Set this start address to 0 too
682 ?LINE 168
TASKING C166/ST10 assembler v8.0r1 Build 256 SN 00096962 Date: Apr 23 2004 Time: 16:27:02 Page: 14
lcd_pg320240
LOC CODE LINE SOURCELINE
018E E6FC1000 683 MOV R12,#010h
0192 E00D 684 MOV R13,#00h
0194 BB86 685 CALLR _lcd_set_reg
686 ; lcd_pg320240.c 169 lcd_set_reg(0x12, 0x00); //Register 12h - Memory Address
Offset. Used for setting memory to a width greater than the display size.
687 ?LINE 169
0196 E6FC1200 688 MOV R12,#012h
019A E00D 689 MOV R13,#00h
019C BB82 690 CALLR _lcd_set_reg
691 ; lcd_pg320240.c 170 //Usually set t
o 0 during initialization and programmed to desired value later.
692 ; lcd_pg320240.c 171 /* This register is used for split screen operation and should
be set to 0 during initialization.
693 ; lcd_pg320240.c 172 Set to maximum (i.e. 0x3FF). */
694 ; lcd_pg320240.c 173 lcd_set_reg(0x13, 0xFF); //Register 13h - Screen 1 Verti
cal Size LSB
695 ?LINE 173
019E E6FC1300 696 MOV R12,#013h
01A2 E6FDFF00 697 MOV R13,#0FFh
01A6 CA00A200 R 698 CALLA cc_UC,_lcd_set_reg
699 ; lcd_pg320240.c 174 lcd_set_reg(0x14, 0x03); //Register 14h - Screen 1 Verti
cal Size MSB
700 ?LINE 174
01AA E6FC1400 701 MOV R12,#014h
01AE E03D 702 MOV R13,#03h
01B0 CA00A200 R 703 CALLA cc_UC,_lcd_set_reg
704 ; lcd_pg320240.c 175
705 ; lcd_pg320240.c 176 /* Look-Up Table In this example the LUT will be programmed in
the register sequence.
706 ; lcd_pg320240.c 177 In practice the LUT would probably be done after the ot
her registers.*/
707 ; lcd_pg320240.c 178 lcd_set_reg(0x15, 0x00); //Register 15h - Look-Up Table
Address. Set to 0x20 to start Gray sequencing at the first LUT entry.
708 ?LINE 178
01B4 E6FC1500 709 MOV R12,#015h
01B8 E00D 710 MOV R13,#00h
01BA CA00A200 R 711 CALLA cc_UC,_lcd_set_reg
712 ; lcd_pg320240.c 179 lcd_set_reg(0x16, 0x00); //Register 16h - Look-Up Table
Bank Select.Set all the banks to 0.
713 ?LINE 179
01BE E6FC1600 714 MOV R12,#016h
01C2 E00D 715 MOV R13,#00h
01C4 CA00A200 R 716 CALLA cc_UC,_lcd_set_reg
717 ; lcd_pg320240.c 180 // At 4BPP this makes no difference however it will affect appe
arance at other color depths.
718 ; lcd_pg320240.c 181 for (i = 0; i < 16; i++) { lcd_set_reg(0x17, i);lcd_set_reg(0x1
7, i);lcd_set_reg(0x17, i);}
719 ?LINE 181
01C8 E00C 720 MOV R12,#00h
01CA B8C0 721 MOV [R0],R12
01CC 0D12 722 JMPR cc_UC,_15
01CE 723 _14:
01CE E6FC1700 724 MOV R12,#017h
01D2 A8D0 725 MOV R13,[R0]
01D4 CA00A200 R 726 CALLA cc_UC,_lcd_set_reg
TASKING C166/ST10 assembler v8.0r1 Build 256 SN 00096962 Date: Apr 23 2004 Time: 16:27:02 Page: 15
lcd_pg320240
LOC CODE LINE SOURCELINE
01D8 E6FC1700 727 MOV R12,#017h
01DC A8D0 728 MOV R13,[R0]
01DE CA00A200 R 729 CALLA cc_UC,_lcd_set_reg
01E2 E6FC1700 730 MOV R12,#017h
01E6 A8D0 731 MOV R13,[R0]
01E8 CA00A200 R 732 CALLA cc_UC,_lcd_set_reg
01EC A8C0 733 MOV R12,[R0]
01EE 08C1 734 ADD R12,#01h
01F0 B8C0 735 MOV [R0],R12
01F2 736 _15:
01F2 A8C0 737 MOV R12,[R0]
01F4 46FC1000 738 CMP R12,#010h
01F8 CDEA 739 JMPR cc_SLT,_14
740 ; lcd_pg320240.c 182 //Register 17h - Look-Up Table Data. Write 16 RGB tripl
ets to setup the LUT for 4BPP operation.
741 ; lcd_pg320240.c 183 //The LUT is 16 elements deep, 4BPP uses all the idices
.
742 ; lcd_pg320240.c 184 lcd_set_reg(0x18, 0x00); //Register 18h - GPIO Configura
tion - set to 0 - '0' configures the GPIO pins for input (power on default)
743 ?LINE 184
01FA E6FC1800 744 MOV R12,#018h
01FE E00D 745 MOV R13,#00h
0200 CA00A200 R 746 CALLA cc_UC,_lcd_set_reg
747 ; lcd_pg320240.c 185 lcd_set_reg(0x19, 0x00); //Register 19h - GPIO Status -
set to 0
748 ?LINE 185
0204 E6FC1900 749 MOV R12,#019h
0208 E00D 750 MOV R13,#00h
020A CA00A200 R 751 CALLA cc_UC,_lcd_set_reg
752 ; lcd_pg320240.c 186
753 ; lcd_pg320240.c 187 lcd_set_reg(0x1A, 0x00); //Register 1Ah - Scratch Pad -
set to 0
754 ?LINE 187
020E E6FC1A00 755 MOV R12,#01Ah
0212 E00D 756 MOV R13,#00h
0214 CA00A200 R 757 CALLA cc_UC,_lcd_set_reg
758 ; lcd_pg320240.c 188 lcd_set_reg(0x1B, 0x00); //Register 1Bh - SwivelView Mod
e - set to 0 - disable SwivelView mode
759 ?LINE 188
0218 E6FC1B00 760 MOV R12,#01Bh
021C E00D 761 MOV R13,#00h
021E CA00A200 R 762 CALLA cc_UC,_lcd_set_reg
763 ; lcd_pg320240.c 189 lcd_set_reg(0x1C, 0xA0); //Register 1Ch - Line Byte Coun
t - set to 0 - Not used by landscape mode
764 ?LINE 189
0222 E6FC1C00 765 MOV R12,#01Ch
0226 E6FDA000 766 MOV R13,#0A0h
022A CA00A200 R 767 CALLA cc_UC,_lcd_set_reg
768 ; lcd_pg320240.c 190 lcd_set_reg(0x1F, 0x00); //Register 1Fh - TestMode - set
to 0
769 ?LINE 190
022E E6FC1F00 770 MOV R12,#01Fh
0232 E00D 771 MOV R13,#00h
0234 CA00A200 R 772 CALLA cc_UC,_lcd_set_reg
773 ; lcd_pg320240.c 191 }
TASKING C166/ST10 assembler v8.0r1 Build 256 SN 00096962 Date: Apr 23 2004 Time: 16:27:02 Page: 16
lcd_pg320240
LOC CODE LINE SOURCELINE
774 ?LINE 191
R 775 ?SYMB '',$,102,1
0238 0802 776 ADD R0,#02h
R 777 ?SYMB '',$,96,0
023A CB00 778 RET
779 _lcd_init ENDP
R 780 ?SYMB '',$,17,191
781 ; lcd_pg320240.c 192
782 ; lcd_pg320240.c 193 void lcd_clear(void)
783 ; lcd_pg320240.c 194 {
784 ?LINE 194
785 PUBLIC _lcd_clear
R 786 ?SYMB 'lcd_clear',_lcd_clear,37,1
787 ?SYMB '',194,8,34
788 _lcd_clear PROC NEAR
789 ?SYMB '',00H,95,0
023C 2802 790 SUB R0,#02h
R 791 ?SYMB '',$,96,2
792 ; Locals:
793 ; i = offset 0
794 ;
795 ; Statics:
796 ;
797 ; CSEs:
798 ;
799 ; lcd_pg320240.c 195 unsigned int i;
800 ?LINE 195
801 ?SYMB 'i',1,98,18
R 802 ?SYMB '-2',$,101,1
803 ; lcd_pg320240.c 196 /* Clear the display, and all of video memory, by writing 40960 byt
es of 0.
804 ; lcd_pg320240.c 197 This is done because an image in display memory is not rotated
with
805 ; lcd_pg320240.c 198 the switch to SwivelView mode we are about to make.*/
806 ; lcd_pg320240.c 199 for (i=0;i < 38400;i++) lcd_write(i,0x00);
807 ?LINE 199
023E E00C 808 MOV R12,#00h
0240 B8C0 809 MOV [R0],R12
0242 0D07 810 JMPR cc_UC,_17
0244 811 _16:
0244 A8C0 812 MOV R12,[R0]
0246 E00D 813 MOV R13,#00h
0248 CA001401 R 814 CALLA cc_UC,_lcd_write
024C A8C0 815 MOV R12,[R0]
024E 08C1 816 ADD R12,#01h
0250 B8C0 817 MOV [R0],R12
0252 818 _17:
0252 A8C0 819 MOV R12,[R0]
0254 46FC0096 820 CMP R12,#09600h
0258 8DF5 821 JMPR cc_ULT,_16
822 ; lcd_pg320240.c 200 }
823 ?LINE 200
R 824 ?SYMB '',$,102,1
025A 0802 825 ADD R0,#02h
R 826 ?SYMB '',$,96,0
TASKING C166/ST10 assembler v8.0r1 Build 256 SN 00096962 Date: Apr 23 2004 Time: 16:27:02 Page: 17
lcd_pg320240
LOC CODE LINE SOURCELINE
025C CB00 827 RET
828 _lcd_clear ENDP
R 829 ?SYMB '',$,17,200
830 LCD_PG320240_3_PR ENDS
831
832 C166_US SECTION DATA WORD GLBUSRSTACK 'CUSTACK'
0000 833 DS 28
834 C166_US ENDS
835
836 C166_INIT SECTION DATA WORD GLOBAL 'CINITROM'
0000 0600 837 DW 06h
0002 00000000 R 838 DPPTR LCD_PG320240_ID_NB_ENTRY,LCD_PG320240_IR_NB_ENTRY
0006 00000000
000A 3000 839 DW 030h
840 C166_INIT ENDS
841
842 C166_DGROUP DGROUP LCD_PG320240_ID_NB
843 REGDEF R0-R15
844 END
total errors: 0, warnings: 0
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