df9177ay.h

how to use display EL16032

/*------------------------------------------------------------
 *	         - uPD78F9177AY.h -
 *
 *	NEC 78K0S microcontroller device uPD78F9177AY.
 *
 *	Declarations of Special Function Registers (SFR) and
 *	interrupt vector addresses.
 *
 *	This header file may be used by both the NEC 78K0/K0S
 *	assembler, A78000 and compiler, ICC78000.
 *
 *	Df9177ay.H created from device file df9177ay.78k [V1.00]
 *	Include file generator E2.10a
 *------------------------------------------------------------*/

#ifndef __IO78f9177ay_INCLUDED
#define __IO78f9177ay_INCLUDED

#if ((__TID__ >> 8) & 0x7F) != 30
#error "Df9177ay.H file for use with A78000 / ICC78000 V3.xx only"
#endif

#if ((__TID__ >> 4) & 0x0F) != 2
#error "Df9177ay.H file for use with A78000 / ICC78000 option -v2 only"
#endif

/*************************************************
 *      SFR macros
 *************************************************/

#define	__IO_NB	0x00010000	/* No bit access */
#define	__IO_WO	0x00020000	/* Write-only    */
#define	__IO_RO	0x00040000	/* Read-only     */

/*************************************************
 *      SFR declarations
 *************************************************/

sfr	P0 	= 0xFF00; 
sfr	P1 	= 0xFF01; 
sfr	P2 	= 0xFF02; 
sfr	P3 	= 0xFF03; 
sfr	P5 	= 0xFF05; 
sfr	P6 	= 0xFF06 | __IO_RO; 
sfrp	MUL0 	= 0xFF10 | __IO_NB | __IO_RO; 
sfr	MUL0L 	= 0xFF10 | __IO_NB | __IO_RO; 
sfr	MUL0H 	= 0xFF11 | __IO_NB | __IO_RO; 
sfrp	ADCR0 	= 0xFF14 | __IO_NB | __IO_RO; 
sfrp	CR90 	= 0xFF16 | __IO_NB | __IO_WO; 
sfr	CR90L 	= 0xFF16 | __IO_NB | __IO_WO; 
sfr	CR90H 	= 0xFF17 | __IO_NB | __IO_WO; 
sfrp	TM90 	= 0xFF18 | __IO_NB | __IO_RO; 
sfr	TM90L 	= 0xFF18 | __IO_NB | __IO_RO; 
sfr	TM90H 	= 0xFF19 | __IO_NB | __IO_RO; 
sfrp	TCP90 	= 0xFF1A | __IO_NB | __IO_RO; 
sfr	TCP90L 	= 0xFF1A | __IO_NB | __IO_RO; 
sfr	TCP90H 	= 0xFF1B | __IO_NB | __IO_RO; 
sfr	PM0 	= 0xFF20; 
sfr	PM1 	= 0xFF21; 
sfr	PM2 	= 0xFF22; 
sfr	PM3 	= 0xFF23; 
sfr	PM5 	= 0xFF25; 
sfr	PUB2 	= 0xFF32; 
sfr	PUB3 	= 0xFF33; 
sfr	TCL2 	= 0xFF42 | __IO_NB; 
sfr	TMC90 	= 0xFF48; 
sfr	BZC90 	= 0xFF49; 
sfr	WTM 	= 0xFF4A; 
sfr	CR80 	= 0xFF50 | __IO_NB | __IO_WO; 
sfr	TM80 	= 0xFF51 | __IO_NB | __IO_RO; 
sfr	TMC80 	= 0xFF53; 
sfr	CR81 	= 0xFF54 | __IO_NB | __IO_WO; 
sfr	TM81 	= 0xFF55 | __IO_NB | __IO_RO; 
sfr	TMC81 	= 0xFF57; 
sfr	CR82 	= 0xFF58 | __IO_NB | __IO_WO; 
sfr	TM82 	= 0xFF59 | __IO_NB | __IO_RO; 
sfr	TMC82 	= 0xFF5B; 
sfr	ASIM20 	= 0xFF70; 
sfr	ASIS20 	= 0xFF71 | __IO_RO; 
sfr	CSIM20 	= 0xFF72; 
sfr	BRGC20 	= 0xFF73 | __IO_NB; 
sfr	RXB20 	= 0xFF74 | __IO_NB | __IO_RO; 
sfr	SIO20 	= 0xFF74 | __IO_NB; 
sfr	TXS20 	= 0xFF74 | __IO_NB | __IO_WO; 
sfr	SMBC0 	= 0xFF78; 
sfr	SMBS0 	= 0xFF79 | __IO_RO; 
sfr	SMBCL0 	= 0xFF7A; 
sfr	SMBSVA0 	= 0xFF7B; 
sfr	SMBM0 	= 0xFF7C; 
sfr	SMBVI0 	= 0xFF7D; 
sfr	SMB0 	= 0xFF7E; 
sfr	ADM0 	= 0xFF80; 
sfr	ADS0 	= 0xFF84; 
sfr	MRA0 	= 0xFFD0 | __IO_WO; 
sfr	MRB0 	= 0xFFD1 | __IO_WO; 
sfr	MULC0 	= 0xFFD2; 
sfr	IF0 	= 0xFFE0; 
sfr	IF1 	= 0xFFE1; 
sfr	MK0 	= 0xFFE4; 
sfr	MK1 	= 0xFFE5; 
sfr	INTM0 	= 0xFFEC | __IO_NB; 
sfr	INTM1 	= 0xFFED | __IO_NB; 
sfr	SCKM 	= 0xFFF0; 
sfr	CSS 	= 0xFFF2; 
sfr	PU0 	= 0xFFF7; 
sfr	WDTM 	= 0xFFF9; 
sfr	OSTS 	= 0xFFFA | __IO_NB; 
sfr	PCC 	= 0xFFFB; 

/*************************************************
 *      SFR bit definitions
 *************************************************/

#define PUB20	 PUB2.0
#define PUB21	 PUB2.1
#define PUB22	 PUB2.2
#define PUB25	 PUB2.5
#define PUB26	 PUB2.6
#define PUB30	 PUB3.0
#define PUB31	 PUB3.1
#define PUB32	 PUB3.2
#define PUB33	 PUB3.3
#define TOE90	 TMC90.0
#define TOF90	 TMC90.6
#define TOE80	 TMC80.0
#define PWME80	 TMC80.6
#define TCE80	 TMC80.7
#define TOE81	 TMC81.0
#define PWME81	 TMC81.6
#define TCE81	 TMC81.7
#define TOE82	 TMC82.0
#define PWME82	 TMC82.6
#define TCE82	 TMC82.7
#define RXE20	 ASIM20.6
#define TXE20	 ASIM20.7
#define CSIE20	 CSIM20.7
#define SPT0	 SMBC0.0
#define STT0	 SMBC0.1
#define ACKE0	 SMBC0.2
#define WTIM0	 SMBC0.3
#define SPIE0	 SMBC0.4
#define WREL0	 SMBC0.5
#define LREL0	 SMBC0.6
#define SMBE0	 SMBC0.7
#define DAD0	 SMBCL0.4
#define CLD0	 SMBCL0.5
#define TOEN0	 SMBM0.2
#define STIE0	 SMBM0.3
#define AWTIM0	 SMBM0.4
#define SCLCTL0	 SMBM0.5
#define ADCS0	 ADM0.7
#define TMIF4	 IF0.0
#define PIF0	 IF0.1
#define PIF1	 IF0.2
#define PIF2	 IF0.3
#define PIF3	 IF0.4
#define SRIF20	 IF0.5
#define STIF20	 IF0.6
#define WTIF	 IF0.7
#define WTIIF	 IF1.0
#define TMIF80	 IF1.1
#define TMIF81	 IF1.2
#define TMIF82	 IF1.3
#define TMIF90	 IF1.4
#define SMBIF0	 IF1.5
#define SMBOVIF0	 IF1.6
#define ADIF0	 IF1.7
#define TMMK4	 MK0.0
#define PMK0	 MK0.1
#define PMK1	 MK0.2
#define PMK2	 MK0.3
#define PMK3	 MK0.4
#define SRMK20	 MK0.5
#define STMK20	 MK0.6
#define WTMK	 MK0.7
#define WTIMK	 MK1.0
#define TMMK80	 MK1.1
#define TMMK81	 MK1.2
#define TMMK82	 MK1.3
#define TMMK90	 MK1.4
#define SMBMK0	 MK1.5
#define SMBOVMK0	 MK1.6
#define ADMK0	 MK1.7
#define PU00	 PU0.0
#define PU01	 PU0.1
#define RUN	 WDTM.7

/*************************************************
 *      Interrupt vector definitions
 *************************************************/

#define	RESET_vect	(0x0000)
#define	INTWDT_vect	(0x0004)
#define	INTWDT_vect	(0x0004)
#define	INTP0_vect	(0x0006)
#define	INTP1_vect	(0x0008)
#define	INTP2_vect	(0x000A)
#define	INTP3_vect	(0x000C)
#define	INTCSI20_vect	(0x000E)
#define	INTSR20_vect	(0x000E)
#define	INTST20_vect	(0x0010)
#define	INTWT_vect	(0x0012)
#define	INTWTI_vect	(0x0014)
#define	INTTM80_vect	(0x0016)
#define	INTTM81_vect	(0x0018)
#define	INTTM82_vect	(0x001A)
#define	INTTM90_vect	(0x001C)
#define	INTSMB0_vect	(0x001E)
#define	INTSMBOV0_vect	(0x0020)
#define	INTAD0_vect	(0x0022)

#endif /* __IO78f9177ay_INCLUDED */