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</p><h3>
16.1.4.5 DMA and non-DMA Devices
</h3>
<p>
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A direct memory access (DMA) device is one that can directly access
(read from and write to) CPU memory, without CPU intervention.
Non-DMA devices cannot directly access CPU memory.
<a name="nx_id_696"></a>
The object of DMA is faster data transfer.
When character drivers perform DMA, they do it to or from the user's
address space.
When block drivers perform DMA, they do it to or from the buffer cache.
<br>
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</p><h2>
16.2 Hardware Activities
</h2>
<p>
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When writing device drivers, you need to consider the following
hardware-related activities:
</p><ul>
<p></p><li>
How a device driver accesses device registers
<p></p></li><li>
How the device uses the registers
<p></p></li><li>
How the device driver interrupts the CPU
</li></ul><p>
The following sections discuss each of these activities as they relate
to device drivers.
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</p><h3>
16.2.1 How a Device Driver Accesses Device Registers
</h3>
<p>
<a name="nx_id_698"></a>
Alpha CPU platforms vary in the mechanisms available to access
device registers.
Some platforms, such as the DEC 4000 and DEC 7000 series, use the
mailbox mechanism.
Other platforms, such as the DEC 3000 series, allow ``direct'' access to
device registers through special address spaces.
The following discussion applies to those platforms that use special
address spaces.
</p><p>
Alpha CPUs can access longwords (32 bits) and quadwords (64 bits)
atomically.
However, many devices have CSRs that are only 16- or 8-bits wide.
Program fragments accessing those CSRs will actually be sequences of
Alpha instructions that fetch longwords and mask out bytes.
For example, for adjacent 16-bit CSRs this longword access is probably
not what is intended.
The fetch of the longword may result in the reading of multiple CSRs,
with unwanted side effects.
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16.2.2 How a Device Uses the Registers
</h3>
<p>
<a name="nx_id_699"></a>
Devices use their registers to report status and to return data.
DMA devices can move data to or from memory directly.
DMA device drivers typically request this type of data transfer by:
</p><ul>
<p></p><li>
Writing a base address and a count of characters
in the device register to specify what data to move
<p></p></li><li>
Setting a bit that requests that the transfer begin
</li></ul><p>
The device requests access to memory and then manages a sequence of data
transfers to memory.
Upon completion of the transfer, the device:
</p><ul>
<p></p><li>
Sets a bit indicating that the transfer is done
<p></p></li><li>
Issues an interrupt
</li></ul><p>
You do not need to know the details of how the
device and the bus interact to handle these transfers of data.
However, you do need to know the exact register fields to use to make
the request.
This information should be in the hardware manual for the device.
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16.2.3 How a Device Driver Interrupts the CPU
</h3>
<p>
<a name="nx_id_700"></a>
The specifics of how interrupts are generated varies from bus to bus and
even from CPU architecture to CPU architecture.
The following is a general description of how interrupts are processed
by the kernel on some systems.
The important point to remember is that the end result of an interrupt
is the calling of the device driver's interrupt handler.
</p><p>
When a device generates an interrupt, it also provides an interrupt
index.
This interrupt index is passed by the bus to the kernel assembly language
interface that does initial handling of interrupts.
That interface uses the interrupt index to determine which entry in the
interrupt vector table contains the address of the interrupt handler for
the device driver that handles this device.
Among other things, the assembly language interface uses that address
to transfer control to the appropriate driver.
Calling the
<tt>handler</tt>
interfaces to dynamically register the interrupt handlers
for a driver causes the
interrupt handlers to be added to this table.
<a href="http://h30097.www3.hp.com/docs/base_doc/DOCUMENTATION/HTML/AA-PUBVD-TE_html/drivertut5.html#SpecMethodforRegIntrptHand">Section 2.4</a>
describes the methods for registering device interrupt handlers.
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16.3 Parts of the System Accessing Hardware
</h2>
<p>
Only two parts of the system access hardware:
</p><ul>
<p></p><li>
The bus support subsystem
<p>
There are specific bus support interfaces that access the device
registers of the bus adapter.
<a name="nx_id_701"></a>
</p><p></p></li><li>
The device driver subsystem
<p>
There are specific device driver interfaces that access the device
registers of specific devices
attached to a controller.
</p></li></ul><p>
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