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</p><h1>16 Hardware Components and Hardware Activities</h1>
<p>
This chapter discusses the hardware environment from the point of view
of the device driver writer.
Specifically, the chapter describes the following hardware components:
</p><ul>
<p></p><li>
The central processing unit (CPU)
<p></p></li><li>
The bus
<p></p></li><li>
The device
</li></ul><p>
</p><p>
The chapter also discusses a variety of hardware activities of
interest to a device driver writer.
<a name="TheHardComp"></a>
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</p><h2>
16.1 Hardware Components
</h2>
<p>
<a href="http://h30097.www3.hp.com/docs/base_doc/DOCUMENTATION/HTML/AA-PUBVD-TE_html/drivertut22.html#HardCompImptoDrv">Figure 16-1</a>
shows the following hardware components:
</p><ul>
<p></p><li>
The central processing unit (CPU)
<p></p></li><li>
Memory
<p></p></li><li>
The bus
<p></p></li><li>
The device
</li></ul><p>
Each of these components is discussed briefly following
<a href="http://h30097.www3.hp.com/docs/base_doc/DOCUMENTATION/HTML/AA-PUBVD-TE_html/drivertut22.html#HardCompImptoDrv">Figure 16-1</a>.
</p><p>
<a name="HardCompImptoDrv"></a>
</p><h3>Figure 16-1: Hardware Components of Interest to a Device Driver Writer</h3>
<p><img src="HW%20activities_files/zk-0565U.gif"></p><p>
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</p><h3>
16.1.1 Central Processing Unit
</h3>
<p>
<a name="nx_id_673"></a>
<a name="nx_id_674"></a>
The central processing unit (CPU) is the main computational unit in a
computer and the one that executes instructions.
The CPU is of interest to device driver writers because its associated
architecture influences the design of the driver.
<a name="nx_id_675"></a>
Writing device drivers for OPENbus architectures in an open systems
environment means that you may need to become familiar with a
variety of CPU architectures, such as Alpha and MIPS.
<a href="http://h30097.www3.hp.com/docs/base_doc/DOCUMENTATION/HTML/AA-PUBVD-TE_html/drivertut6.html#CPUIssues">Section 3.1</a>
describes the CPU issues that influence the design of device drivers.
<a name="Memory"></a>
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</p><h3>
16.1.2 Memory
</h3>
<p>
<a name="nx_id_676"></a>
<a href="http://h30097.www3.hp.com/docs/base_doc/DOCUMENTATION/HTML/AA-PUBVD-TE_html/drivertut22.html#HardCompImptoDrv">Figure 16-1</a>
shows that both the kernel and device drivers reside in memory, as does the
kernel interrupt code that determines what driver will
handle each interrupt from
a device.
The device driver accesses device registers (often referred to as
control status register or CSR addresses) as though they were in
memory; however, these registers are not really in memory but are
located in the device.
<a href="http://h30097.www3.hp.com/docs/base_doc/DOCUMENTATION/HTML/AA-PUBVD-TE_html/drivertut22.html#HardCompImptoDrv">Figure 16-1</a>
shows this arrangment by identifying a virtual location for the device
registers.
The hardware manual for the device you are writing the driver for should
describe these device register addresses or offsets.
</p><p>
<a name="nx_id_677"></a>
For Digital-implemented buses,
the address is encoded in the form of an I/O handle.
The data type
<tt>io_handle_t</tt>
represents this I/O handle.
The I/O handle for the TURBOchannel bus represents an address that is
based on the slot.
The bus configuration code passes the I/O handle to the device driver
through the
<tt>probe</tt>
interface.
</p><p>
A device driver that operates on the EISA, PCI, or TURBOchannel bus accesses
the device registers by referencing this I/O handle in calls to
<tt>read_io_port</tt>
and
<tt>write_io_port</tt>.
See the bus-specific book to determine how the bus you are writing the
driver for passes this I/O handle to the
<tt>probe</tt>
interface.
<a name="TheBus"></a>
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</p><h3>
16.1.3 Bus
</h3>
<p>
<a name="nx_id_678"></a>
The bus is the path for all communication among the CPU, memory, and
devices.
Thus, when a device driver reads from or writes to a device's
registers, the information transfer is by way of the bus.
If you write device drivers for OPEN systems, you will probably need to
know about a variety of buses, including the following:
</p><ul>
<p></p><li>
EISA
<p></p></li><li>
ISA
<p></p></li><li>
PCI
<p></p></li><li>
SCSI
<p></p></li><li>
TURBOchannel
<p></p></li><li>
VMEbus
</li></ul><p>
</p><p>
There are three situations when the bus is of concern to you:
</p><ul>
<p></p><li>
When specifying which bus a device is on
<p></p></li><li>
When writing
<tt>probe</tt>
and
<tt>slave</tt>
interfaces
<p></p></li><li>
When a device does direct memory access (DMA)
</li></ul><p>
Each of these situations is briefly considered in the following
sections.
<a name="SpecifyBusDeviceIsOn"></a>
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</p><h3>
16.1.3.1 Specifying Which Bus a Device Is On
</h3>
<p>
<a name="nx_id_679"></a>
For the most part, you can think of the bus as a
single path, but at kernel configuration time this view is not adequate.
The bus, as used in this book, includes:
</p><ul>
<p></p><li>
The system bus
<p></p></li><li>
Other buses attached to the system bus, for example, a
VMEbus
</li></ul><p>
</p><p>
When adding a device driver, you very well may be adding a device to the
system.
If you are, you will need to know what bus to attach its device
controller to.
</p><p>
Digital UNIX
provides the
<tt>create_controller_struct</tt>
and
<tt>create_device_struct</tt>
interfaces.
These interfaces create the
<tt>controller</tt>
and
<tt>device</tt>
structures associated with your device driver.
<a href="http://h30097.www3.hp.com/docs/base_doc/DOCUMENTATION/HTML/AA-PUBVD-TE_html/drivertut10.html#UsingCreRtnstoRegContrlDevInfo">Section 6.6.4.3</a>
shows you how to use these interfaces.
</p><p>
</p><p>
These interfaces take one argument: a
<tt>controller_config</tt>
structure for
<tt>create_controller_struct</tt>
and a
<tt>device_config</tt>
structure for
<tt>create_device_struct</tt>.
When you supply the appropriate information in these structures, the
<tt>create_controller_struct</tt>
and
<tt>create_device_struct</tt>
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