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游戏玩家通过控制PS/2键盘上的方向键

  Destination:       v/red_out (FF)
  Source Clock:      divClk_50/clk:Q rising
  Destination Clock: divClk_50/clk:Q rising

  Data Path: v/pixel_row_4_1 to v/red_out
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q             11   0.626   1.267  v/pixel_row_4_1 (v/pixel_row_4_1)
     LUT4:I0->O            1   0.479   0.976  men2/Mrom__n0083_inst_mux_f5_4811_F_SW0 (N2065)
     LUT3_L:I0->LO         1   0.479   0.000  men2/Mrom__n0083_inst_mux_f5_4811_F (N2183)
     MUXF5:I0->O           1   0.314   0.851  men2/Mrom__n0083_inst_mux_f5_4811 (men2/_n0083<7>)
     LUT3_L:I1->LO         1   0.479   0.000  men2/col<1>_rn_21_F (N2205)
     MUXF5:I0->O           3   0.314   0.830  men2/col<1>_rn_21 (men2/MUX_BLOCK_col<1>_MUXF51)
     LUT3:I2->O            1   0.479   0.704  men2/col<5>1_SW1_SW0 (N2142)
     LUT4_L:I3->LO         1   0.479   0.000  men1/char<0>775_SW1_G (N2374)
     MUXF5:I1->O           3   0.314   0.941  men1/char<0>775_SW1 (N1595)
     LUT4_D:I1->O          3   0.479   0.794  mux2/c<0>1 (char<0>)
     LUT4_L:I3->LO         1   0.479   0.159  generator/s_mux<2>257_SW0 (N1591)
     LUT4_L:I2->LO         1   0.479   0.000  v/_n00051 (v/_n0005)
     FD:D                      0.176          v/red_out
    ----------------------------------------
    Total                     12.098ns (5.576ns logic, 6.522ns route)
                                       (46.1% logic, 53.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'div23p/clk23b:Q'
  Clock period: 4.841ns (frequency: 206.577MHz)
  Total number of paths / destination ports: 36 / 6
-------------------------------------------------------------------------
Delay:               4.841ns (Levels of Logic = 2)
  Source:            lights/dir (FF)
  Destination:       lights/dir (FF)
  Source Clock:      div23p/clk23b:Q rising
  Destination Clock: div23p/clk23b:Q rising

  Data Path: lights/dir to lights/dir
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             7   0.626   1.201  lights/dir (lights/dir)
     LUT4:I0->O            1   0.479   0.851  lights/_n00161_SW0 (N31)
     LUT3:I1->O            1   0.479   0.681  lights/_n00161 (lights/_n0016)
     FDRE:CE                   0.524          lights/dir
    ----------------------------------------
    Total                      4.841ns (2.108ns logic, 2.733ns route)
                                       (43.5% logic, 56.5% route)

=========================================================================
Timing constraint: Default period analysis for Clock 't/clk_1hz:Q'
  Clock period: 9.050ns (frequency: 110.500MHz)
  Total number of paths / destination ports: 296 / 44
-------------------------------------------------------------------------
Delay:               9.050ns (Levels of Logic = 6)
  Source:            t/d1_3 (FF)
  Destination:       t/d4_3 (FF)
  Source Clock:      t/clk_1hz:Q rising
  Destination Clock: t/clk_1hz:Q rising

  Data Path: t/d1_3 to t/d4_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             4   0.626   1.074  t/d1_3 (t/d1_3)
     LUT4:I0->O            2   0.479   0.804  t/_n00121 (t/_n0012)
     LUT3_L:I2->LO         1   0.479   0.123  t/Ker0_SW0 (N21)
     LUT4:I3->O            6   0.479   0.876  t/Ker0 (t/N01)
     LUT4_D:I3->O          5   0.479   0.842  t/Ker1 (t/N11)
     LUT3_L:I2->LO         1   0.479   0.159  t/_n0002_SW0 (N23)
     LUT4:I2->O            4   0.479   0.779  t/_n0002 (t/_n0002)
     FDRE:R                    0.892          t/d4_0
    ----------------------------------------
    Total                      9.050ns (4.392ns logic, 4.658ns route)
                                       (48.5% logic, 51.5% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'ps2/KCI:Q'
  Clock period: 9.909ns (frequency: 100.914MHz)
  Total number of paths / destination ports: 97 / 34
-------------------------------------------------------------------------
Delay:               4.955ns (Levels of Logic = 2)
  Source:            ps2/shiftRegSig2_5 (FF)
  Destination:       ps2/WaitReg_7 (FF)
  Source Clock:      ps2/KCI:Q falling
  Destination Clock: ps2/KCI:Q rising

  Data Path: ps2/shiftRegSig2_5 to ps2/WaitReg_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD_1:C->Q             2   0.626   1.040  ps2/shiftRegSig2_5 (ps2/shiftRegSig2_5)
     LUT4:I0->O            1   0.479   0.851  ps2/_n00014 (CHOICE1051)
     LUT2:I1->O            9   0.479   0.955  ps2/_n000118 (ps2/_n0001)
     FDCE:CE                   0.524          ps2/WaitReg_1
    ----------------------------------------
    Total                      4.955ns (2.108ns logic, 2.847ns route)
                                       (42.5% logic, 57.5% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'ps2/clkDiv_3:Q'
  Clock period: 1.483ns (frequency: 674.377MHz)
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Delay:               1.483ns (Levels of Logic = 0)
  Source:            ps2/DFF1 (FF)
  Destination:       ps2/KDI (FF)
  Source Clock:      ps2/clkDiv_3:Q rising
  Destination Clock: ps2/clkDiv_3:Q rising

  Data Path: ps2/DFF1 to ps2/KDI
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               1   0.626   0.681  ps2/DFF1 (ps2/DFF1)
     FD:D                      0.176          ps2/KDI
    ----------------------------------------
    Total                      1.483ns (0.802ns logic, 0.681ns route)
                                       (54.1% logic, 45.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clock_50Mhz'
  Total number of paths / destination ports: 14 / 14
-------------------------------------------------------------------------
Offset:              3.926ns (Levels of Logic = 2)
  Source:            reset (PAD)
  Destination:       validate_position/S (FF)
  Destination Clock: clock_50Mhz rising

  Data Path: reset to validate_position/S
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            24   0.715   1.527  reset_IBUF (reset_IBUF)
     INV:I->O              1   0.479   0.681  validate_position/S_ClkEn_INV1_INV_0 (validate_position/S_N0)
     FDE:CE                    0.524          validate_position/S
    ----------------------------------------
    Total                      3.926ns (1.718ns logic, 2.208ns route)
                                       (43.8% logic, 56.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'div23p/clk23b:Q'
  Total number of paths / destination ports: 5 / 5
-------------------------------------------------------------------------
Offset:              3.134ns (Levels of Logic = 1)
  Source:            reset (PAD)
  Destination:       lights/dir (FF)
  Destination Clock: div23p/clk23b:Q rising

  Data Path: reset to lights/dir
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            24   0.715   1.527  reset_IBUF (reset_IBUF)
     FDRE:R                    0.892          lights/led_FFd3
    ----------------------------------------
    Total                      3.134ns (1.607ns logic, 1.527ns route)
                                       (51.3% logic, 48.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 't/clk_1hz:Q'
  Total number of paths / destination ports: 16 / 16
-------------------------------------------------------------------------
Offset:              4.688ns (Levels of Logic = 2)
  Source:            reset (PAD)
  Destination:       t/d1_3 (FF)
  Destination Clock: t/clk_1hz:Q rising

  Data Path: reset to t/d1_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            24   0.715   1.822  reset_IBUF (reset_IBUF)
     LUT3:I0->O            4   0.479   0.779  t/_n00081 (t/_n0008)
     FDRE:R                    0.892          t/d1_0
    ----------------------------------------
    Total                      4.688ns (2.086ns logic, 2.602ns route)
                                       (44.5% logic, 55.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'ps2/clkDiv_3:Q'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              1.572ns (Levels of Logic = 1)
  Source:            KD (PAD)
  Destination:       ps2/DFF1 (FF)
  Destination Clock: ps2/clkDiv_3:Q rising

  Data Path: KD to ps2/DFF1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.715   0.681  KD_IBUF (KD_IBUF)
     FD:D                      0.176          ps2/DFF1
    ----------------------------------------
    Total                      1.572ns (0.891ns logic, 0.681ns route)
                                       (56.7% logic, 43.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'display/divclk/clk_16:Q'
  Total number of paths / destination ports: 92 / 11
-------------------------------------------------------------------------
Offset:              9.934ns (Levels of Logic = 4)
  Source:            display/num/val_1 (FF)
  Destination:       ca (PAD)
  Source Clock:      display/divclk/clk_16:Q rising

  Data Path: display/num/val_1 to ca
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              12   0.626   1.245  display/num/val_1 (display/num/val_1)
     LUT3:I0->O            1   0.479   0.000  an1_an1_rn_1111_G (N2188)
     MUXF5:I1->O           7   0.314   1.201  an1_an1_rn_1111 (display/mux_out<2>)
     LUT4:I0->O            1   0.479   0.681  display/rom/Mrom_digit_inst_lut4_51 (cc_OBUF)
     OBUF:I->O                 4.909          cc_OBUF (cc)
    ----------------------------------------
    Total                      9.934ns (6.807ns logic, 3.127ns route)
                                       (68.5% logic, 31.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 't/clk_1hz:Q'
  Total number of paths / destination ports: 112 / 7
-------------------------------------------------------------------------
Offset:              9.712ns (Levels of Logic = 4)
  Source:            t/d4_0 (FF)
  Destination:       ca (PAD)
  Source Clock:      t/clk_1hz:Q rising

  Data Path: t/d4_0 to ca
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             6   0.626   1.023  t/d4_0 (t/d4_0)
     LUT3:I1->O            1   0.479   0.000  an1_an1111_F (N2185)
     MUXF5:I0->O           7   0.314   1.201  an1_an1111 (display/mux_out<0>)
     LUT4:I0->O            1   0.479   0.681  display/rom/Mrom_digit_inst_lut4_71 (ca_OBUF)
     OBUF:I->O                 4.909          ca_OBUF (ca)
    ----------------------------------------
    Total                      9.712ns (6.807ns logic, 2.904ns route)
                                       (70.1% logic, 29.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'div23p/clk23b:Q'
  Total number of paths / destination ports: 29 / 8
-------------------------------------------------------------------------
Offset:              8.041ns (Levels of Logic = 2)
  Source:            lights/led_FFd2 (FF)
  Destination:       led4 (PAD)
  Source Clock:      div23p/clk23b:Q rising

  Data Path: lights/led_FFd2 to led4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q            16   0.626   1.346  lights/led_FFd2 (lights/led_FFd2)
     LUT4:I0->O            1   0.479   0.681  lights/led41 (led4_OBUF)
     OBUF:I->O                 4.909          led4_OBUF (led4)
    ----------------------------------------
    Total                      8.041ns (6.014ns logic, 2.027ns route)
                                       (74.8% logic, 25.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'divClk_50/clk:Q'
  Total number of paths / destination ports: 5 / 5
-------------------------------------------------------------------------
Offset:              6.216ns (Levels of Logic = 1)
  Source:            v/vert_sync_out (FF)
  Destination:       vert_sync_out (PAD)
  Source Clock:      divClk_50/clk:Q rising

  Data Path: v/vert_sync_out to vert_sync_out
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               1   0.626   0.681  v/vert_sync_out (v/vert_sync_out)
     OBUF:I->O                 4.909          vert_sync_out_OBUF (vert_sync_out)
    ----------------------------------------
    Total                      6.216ns (5.535ns logic, 0.681ns route)
                                       (89.0% logic, 11.0% route)

=========================================================================
CPU : 40.14 / 40.56 s | Elapsed : 40.00 / 41.00 s
 
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Total memory usage is 109248 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    5 (   0 filtered)
Number of infos    :    2 (   0 filtered)