top_zoumigong.syr

游戏玩家通过控制PS/2键盘上的方向键

 32x120-bit ROM                    : 1
# Adders/Subtractors               : 2
 6-bit addsub                      : 2
# Counters                         : 11
 10-bit up counter                 : 2
 17-bit up counter                 : 1
 2-bit up counter                  : 1
 32-bit up counter                 : 2
 4-bit up counter                  : 5
# Registers                        : 50
 1-bit register                    : 41
 10-bit register                   : 2
 2-bit register                    : 1
 6-bit register                    : 4
 8-bit register                    : 2
# Latches                          : 1
 1-bit latch                       : 1
# Shift Registers                  : 2
 3-bit shift register              : 1
 4-bit shift register              : 1
# Comparators                      : 10
 11-bit comparator greatequal      : 4
 11-bit comparator lessequal       : 4
 6-bit comparator equal            : 2
# Multiplexers                     : 11
 1-bit 4-to-1 multiplexer          : 5
 1-bit 40-to-1 multiplexer         : 1
 3-bit 16-to-1 multiplexer         : 3
 3-bit 8-to-1 multiplexer          : 1
 4-bit 4-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <top_zoumigong> ...

Optimizing unit <newPositions> ...

Optimizing unit <vga> ...

Optimizing unit <light> ...

Optimizing unit <mux2_1_6bits> ...

Optimizing unit <mux2_3bits> ...

Optimizing unit <rom_labirint> ...

Optimizing unit <rom2_labirint> ...

Optimizing unit <timer> ...

Optimizing unit <keyboard> ...

Optimizing unit <validate_positions> ...

Optimizing unit <div_clk_6hz> ...

Optimizing unit <char_generator> ...
Loading device for application Rf_Device from file '3s400.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_zoumigong, actual ratio is 9.
FlipFlop new_pos/NR_0 has been replicated 14 time(s)
FlipFlop new_pos/NR_1 has been replicated 15 time(s)
FlipFlop new_pos/NR_2 has been replicated 13 time(s)
FlipFlop new_pos/NR_3 has been replicated 13 time(s)
FlipFlop new_pos/NR_4 has been replicated 12 time(s)
FlipFlop new_pos/o has been replicated 9 time(s)
FlipFlop v/pixel_row_4 has been replicated 12 time(s)
FlipFlop v/pixel_row_5 has been replicated 14 time(s)
FlipFlop v/pixel_row_6 has been replicated 15 time(s)
FlipFlop v/pixel_row_7 has been replicated 13 time(s)
FlipFlop v/pixel_row_8 has been replicated 12 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : top_zoumigong.ngr
Top Level Output File Name         : top_zoumigong
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 30

Macro Statistics :
# ROMs                             : 6
#      16x48-bit ROM               : 3
#      16x8-bit ROM                : 1
#      30x39-bit ROM               : 1
#      32x120-bit ROM              : 1
# Registers                        : 67
#      1-bit register              : 49
#      10-bit register             : 13
#      2-bit register              : 1
#      6-bit register              : 2
#      8-bit register              : 2
# Shift Registers                  : 2
#      3-bit shift register        : 1
#      4-bit shift register        : 1
# Multiplexers                     : 11
#      1-bit 4-to-1 multiplexer    : 5
#      1-bit 40-to-1 multiplexer   : 1
#      3-bit 16-to-1 multiplexer   : 3
#      3-bit 8-to-1 multiplexer    : 1
#      4-bit 4-to-1 multiplexer    : 1
# Adders/Subtractors               : 13
#      10-bit adder                : 11
#      6-bit addsub                : 2
# Comparators                      : 10
#      11-bit comparator greatequal: 4
#      11-bit comparator lessequal : 4
#      6-bit comparator equal      : 2

Cell Usage :
# BELS                             : 1233
#      GND                         : 1
#      INV                         : 15
#      LUT1                        : 96
#      LUT2                        : 24
#      LUT2_L                      : 14
#      LUT3                        : 79
#      LUT3_D                      : 8
#      LUT3_L                      : 154
#      LUT4                        : 371
#      LUT4_D                      : 7
#      LUT4_L                      : 99
#      MUXCY                       : 112
#      MUXF5                       : 127
#      MUXF6                       : 11
#      MUXF7                       : 5
#      MUXF8                       : 1
#      VCC                         : 1
#      XORCY                       : 108
# FlipFlops/Latches                : 371
#      FD                          : 32
#      FD_1                        : 14
#      FDCE                        : 9
#      FDE                         : 176
#      FDE_1                       : 2
#      FDR                         : 93
#      FDRE                        : 42
#      FDSE                        : 2
#      LDC                         : 1
# Shifters                         : 2
#      SRL16E_1                    : 2
# Clock Buffers                    : 4
#      BUFG                        : 3
#      BUFGP                       : 1
# IO Buffers                       : 29
#      IBUF                        : 3
#      OBUF                        : 26
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-5 

 Number of Slices:                     470  out of   3584    13%  
 Number of Slice Flip Flops:           371  out of   7168     5%  
 Number of 4 input LUTs:               854  out of   7168    11%  
 Number of bonded IOBs:                 30  out of    141    21%  
 Number of GCLKs:                        4  out of      8    50%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
validate_position/done:Q           | NONE                   | 1     |
clock_50Mhz                        | BUFGP                  | 200   |
display/divclk/clk_16:Q            | NONE                   | 4     |
ps2/RDY:Q                          | BUFG                   | 1     |
divClk_50/clk:Q                    | BUFG                   | 115   |
div23p/clk23b:Q                    | NONE                   | 5     |
t/clk_1hz:Q                        | NONE                   | 16    |
ps2/KCI:Q                          | BUFG                   | 27    |
ps2/clkDiv_3:Q                     | NONE                   | 4     |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 12.187ns (Maximum Frequency: 82.057MHz)
   Minimum input arrival time before clock: 4.688ns
   Maximum output required time after clock: 9.934ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'validate_position/done:Q'
  Clock period: 2.301ns (frequency: 434.622MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               2.301ns (Levels of Logic = 0)
  Source:            select/sel (FF)
  Destination:       select/sel (FF)
  Source Clock:      validate_position/done:Q rising
  Destination Clock: validate_position/done:Q rising

  Data Path: select/sel to select/sel
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              5   0.626   0.783  select/sel (select/sel)
     FDR:R                     0.892          select/sel
    ----------------------------------------
    Total                      2.301ns (1.518ns logic, 0.783ns route)
                                       (66.0% logic, 34.0% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clock_50Mhz'
  Clock period: 12.187ns (frequency: 82.057MHz)
  Total number of paths / destination ports: 12572 / 358
-------------------------------------------------------------------------
Delay:               12.187ns (Levels of Logic = 12)
  Source:            new_pos/NR_2_2 (FF)
  Destination:       validate_position/done (FF)
  Source Clock:      clock_50Mhz rising
  Destination Clock: clock_50Mhz rising

  Data Path: new_pos/NR_2_2 to validate_position/done
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              9   0.626   1.250  new_pos/NR_2_2 (new_pos/NR_22)
     LUT4:I0->O            1   0.479   0.976  men2/Mrom__n0083_inst_mux_f5_4911_F_SW1 (N1940)
     LUT3_L:I0->LO         1   0.479   0.000  men2/Mrom__n0083_inst_mux_f5_4911_G (N2322)
     MUXF5:I1->O           1   0.314   0.851  men2/Mrom__n0083_inst_mux_f5_4911 (men2/_n0083<8>)
     LUT3_L:I1->LO         1   0.479   0.000  men2/col<3> (men2/MUX_BLOCK_N2)
     MUXF5:I1->O           1   0.314   0.000  men2/col<4> (men2/MUX_BLOCK_col<4>_MUXF5)
     MUXF6:I1->O           1   0.298   0.000  men2/col<0> (men2/MUX_BLOCK_col<0>_MUXF6)
     MUXF7:I1->O           1   0.298   0.000  men2/col<1> (men2/MUX_BLOCK_col<1>_MUXF7)
     MUXF8:I1->O           2   0.298   0.915  men2/col<2> (men2/MUX_BLOCK_col<2>_MUXF8)
     LUT3_L:I1->LO         1   0.479   0.000  men1/char<0>775_SW01_G (N2200)
     MUXF5:I1->O           4   0.314   0.949  men1/char<0>775_SW01 (N1594)
     LUT2:I1->O            1   0.479   0.704  validate_position/_n00071_SW0 (N2083)
     LUT4:I3->O            1   0.479   0.681  validate_position/_n00071 (validate_position/_n0007)
     FDRE:CE                   0.524          validate_position/done
    ----------------------------------------
    Total                     12.187ns (5.860ns logic, 6.327ns route)
                                       (48.1% logic, 51.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'display/divclk/clk_16:Q'
  Clock period: 2.347ns (frequency: 426.085MHz)
  Total number of paths / destination ports: 5 / 4
-------------------------------------------------------------------------
Delay:               2.347ns (Levels of Logic = 1)
  Source:            display/num/val1_0 (FF)
  Destination:       display/num/val1_1 (FF)
  Source Clock:      display/divclk/clk_16:Q rising
  Destination Clock: display/divclk/clk_16:Q rising

  Data Path: display/num/val1_0 to display/num/val1_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   0.626   1.066  display/num/val1_0 (display/num/val1_0)
     LUT2:I0->O            1   0.479   0.000  display/num/val1_Madd__n0000_Mxor_Result<1>_Result1 (display/num/val1__n0000<1>)
     FD:D                      0.176          display/num/val1_1
    ----------------------------------------
    Total                      2.347ns (1.281ns logic, 1.066ns route)
                                       (54.6% logic, 45.4% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'divClk_50/clk:Q'
  Clock period: 12.098ns (frequency: 82.660MHz)
  Total number of paths / destination ports: 6446 / 231
-------------------------------------------------------------------------
Delay:               12.098ns (Levels of Logic = 11)
  Source:            v/pixel_row_4_1 (FF)