top_zoumigong.syr

游戏玩家通过控制PS/2键盘上的方向键

Synthesizing Unit <div_clk_381hz>.
    Related source file is "div_clk_381hz.v".
    Found 17-bit up counter for signal <clk>.
    Summary:
	inferred   1 Counter(s).
Unit <div_clk_381hz> synthesized.


Synthesizing Unit <mux8_1_3bits>.
    Related source file is "mux8_1_3bits.v".
    Found 3-bit 8-to-1 multiplexer for signal <o>.
    Summary:
	inferred   3 Multiplexer(s).
Unit <mux8_1_3bits> synthesized.


Synthesizing Unit <rom_door_char>.
    Related source file is "rom_door_char.v".
    Found 16x48-bit ROM for signal <rom_line>.
    Found 3-bit 16-to-1 multiplexer for signal <color>.
    Summary:
	inferred   1 ROM(s).
	inferred   3 Multiplexer(s).
Unit <rom_door_char> synthesized.


Synthesizing Unit <rom_human_char>.
    Related source file is "rom_human_char.v".
    Found 16x48-bit ROM for signal <rom_line>.
    Found 3-bit 16-to-1 multiplexer for signal <color>.
    Summary:
	inferred   1 ROM(s).
	inferred   3 Multiplexer(s).
Unit <rom_human_char> synthesized.


Synthesizing Unit <rom_wall_char>.
    Related source file is "rom_wall_char.v".
    Found 16x48-bit ROM for signal <rom_line>.
    Found 3-bit 16-to-1 multiplexer for signal <color>.
    Summary:
	inferred   1 ROM(s).
	inferred   3 Multiplexer(s).
Unit <rom_wall_char> synthesized.


Synthesizing Unit <rom_empty_char>.
    Related source file is "rom_empty_char.v".
Unit <rom_empty_char> synthesized.


Synthesizing Unit <timer_enable>.
    Related source file is "timer_enable.v".
WARNING:Xst:737 - Found 1-bit latch for signal <enable>.
Unit <timer_enable> synthesized.


Synthesizing Unit <timer>.
    Related source file is "timer.v".
    Found 4-bit up counter for signal <d1>.
    Found 4-bit up counter for signal <d2>.
    Found 4-bit up counter for signal <d3>.
    Found 4-bit up counter for signal <d4>.
    Found 1-bit register for signal <clk_1hz>.
    Found 32-bit up counter for signal <i>.
    Summary:
	inferred   5 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <timer> synthesized.


Synthesizing Unit <seg7_display>.
    Related source file is "seg7_display.v".
Unit <seg7_display> synthesized.


Synthesizing Unit <light>.
    Related source file is "light.v".
    Found finite state machine <FSM_0> for signal <led>.
    -----------------------------------------------------------------------
    | States             | 11                                             |
    | Transitions        | 22                                             |
    | Inputs             | 1                                              |
    | Outputs            | 10                                             |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | done (positive)                                |
    | Reset              | reset (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 00000000                                       |
    | Power Up State     | 00000000                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <dir>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 D-type flip-flop(s).
Unit <light> synthesized.


Synthesizing Unit <div_clk_6hz>.
    Related source file is "div_clk_6hz.v".
    Found 1-bit register for signal <clk23b>.
    Found 32-bit up counter for signal <i>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <div_clk_6hz> synthesized.


Synthesizing Unit <validate_positions>.
    Related source file is "validate_positions.v".
    Found 1-bit register for signal <S>.
    Found 1-bit register for signal <done>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <validate_positions> synthesized.


Synthesizing Unit <newPositions>.
    Related source file is "newPositions.v".
    Found 6-bit register for signal <NC>.
    Found 6-bit register for signal <NR>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 39.
    Found 6-bit addsub for signal <$n0007>.
    Found 6-bit addsub for signal <$n0008>.
    Found 1-bit register for signal <o>.
    Summary:
	inferred  13 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   1 Multiplexer(s).
Unit <newPositions> synthesized.


Synthesizing Unit <keyboard>.
    Related source file is "D:/ASIC设计/zoumigong/keyboard.vhd".
    Found 1-bit register for signal <RDY>.
    Found 4-bit up counter for signal <clkDiv>.
    Found 1-bit register for signal <DFF1>.
    Found 1-bit register for signal <DFF2>.
    Found 1-bit register for signal <KCI>.
    Found 1-bit register for signal <KDI>.
    Found 8-bit register for signal <lastvalue>.
    Found 1-bit register for signal <receivedChar>.
    Found 3-bit shift register for signal <shiftRegSig1<8>>.
    Found 7-bit register for signal <shiftRegSig1<7:1>>.
    Found 4-bit shift register for signal <shiftRegSig2<8>>.
    Found 7-bit register for signal <shiftRegSig2<7:1>>.
    Found 8-bit register for signal <WaitReg>.
    Summary:
	inferred   1 Counter(s).
	inferred  36 D-type flip-flop(s).
	inferred   2 Shift register(s).
Unit <keyboard> synthesized.


Synthesizing Unit <char_generator>.
    Related source file is "char_generator.v".
    Found 6-bit comparator equal for signal <$n0001> created at line 47.
    Found 6-bit comparator equal for signal <$n0002> created at line 47.
    Summary:
	inferred   2 Comparator(s).
Unit <char_generator> synthesized.


Synthesizing Unit <reg_6bits>.
    Related source file is "reg_6bits.v".
    Found 6-bit register for signal <y>.
Unit <reg_6bits> synthesized.


Synthesizing Unit <mux2_3bits>.
    Related source file is "mux2_3bits.v".
Unit <mux2_3bits> synthesized.


Synthesizing Unit <select_rom>.
    Related source file is "select_rom.v".
    Found 1-bit register for signal <sel>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <select_rom> synthesized.


Synthesizing Unit <rom2_labirint>.
    Related source file is "D:/ASIC设计/zoumigong/rom2_labirint.vhd".
    Found 30x39-bit ROM for signal <$n0083>.
    Found 1-bit 40-to-1 multiplexer for signal <char<0>>.
    Summary:
	inferred   1 ROM(s).
	inferred   1 Multiplexer(s).
Unit <rom2_labirint> synthesized.


Synthesizing Unit <rom_labirint>.
    Related source file is "rom_labirint.v".
    Found 32x120-bit ROM for signal <$n0000>.
    Summary:
	inferred   1 ROM(s).
Unit <rom_labirint> synthesized.


Synthesizing Unit <mux2_1_6bits>.
    Related source file is "mux2_1_6bits.v".
Unit <mux2_1_6bits> synthesized.


Synthesizing Unit <div16>.
    Related source file is "div16.v".
WARNING:Xst:647 - Input <pixel_col<3:0>> is never used.
WARNING:Xst:647 - Input <pixel_row<3:0>> is never used.
Unit <div16> synthesized.


Synthesizing Unit <vga>.
    Related source file is "D:/ASIC设计/zoumigong/vga.vhd".
    Found 1-bit register for signal <vert_sync_out>.
    Found 10-bit register for signal <pixel_row>.
    Found 1-bit register for signal <blue_out>.
    Found 1-bit register for signal <red_out>.
    Found 10-bit register for signal <pixel_column>.
    Found 1-bit register for signal <horiz_sync_out>.
    Found 1-bit register for signal <green_out>.
    Found 11-bit comparator lessequal for signal <$n0007> created at line 77.
    Found 11-bit comparator lessequal for signal <$n0013> created at line 71.
    Found 11-bit comparator greatequal for signal <$n0017> created at line 59.
    Found 11-bit comparator greatequal for signal <$n0018> created at line 59.
    Found 11-bit comparator lessequal for signal <$n0019> created at line 65.
    Found 11-bit comparator greatequal for signal <$n0020> created at line 65.
    Found 11-bit comparator lessequal for signal <$n0021> created at line 53.
    Found 11-bit comparator greatequal for signal <$n0022> created at line 53.
    Found 10-bit up counter for signal <h_count>.
    Found 1-bit register for signal <horiz_sync>.
    Found 10-bit up counter for signal <v_count>.
    Found 1-bit register for signal <vert_sync>.
    Found 1-bit register for signal <video_on_h>.
    Found 1-bit register for signal <video_on_v>.
    Summary:
	inferred   2 Counter(s).
	inferred  29 D-type flip-flop(s).
	inferred   8 Comparator(s).
Unit <vga> synthesized.


Synthesizing Unit <div_clk_25Mhz>.
    Related source file is "div_clk_25Mhz.v".
    Found 1-bit register for signal <clk>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <div_clk_25Mhz> synthesized.


Synthesizing Unit <top_zoumigong>.
    Related source file is "top_zoumigong.v".
Unit <top_zoumigong> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <led[1:4]> with sequential encoding.
----------------------
 State    | Encoding
----------------------
 00000000 | 0000
 10000000 | 0001
 11000000 | 0010
 11100000 | 0011
 01110000 | 0100
 00111000 | 0101
 00011100 | 0110
 00000111 | 0111
 00000011 | 1000
 00000001 | 1001
 00001110 | 1010
----------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 6
 16x48-bit ROM                     : 3
 16x8-bit ROM                      : 1
 30x39-bit ROM                     : 1