📄 light.syr
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Release 7.1i - xst H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.44 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.44 s | Elapsed : 0.00 / 0.00 s --> Reading design: light.prjTABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 5) Advanced HDL Synthesis 5.1) HDL Synthesis Report 6) Low Level Synthesis 7) Final Report 7.1) Device utilization summary 7.2) TIMING REPORT=========================================================================* Synthesis Options Summary *=========================================================================---- Source ParametersInput File Name : "light.prj"Input Format : mixedIgnore Synthesis Constraint File : NO---- Target ParametersOutput File Name : "light"Output Format : NGCTarget Device : xc3s400-5-pq208---- Source OptionsTop Module Name : lightAutomatic FSM Extraction : YESFSM Encoding Algorithm : AutoFSM Style : lutRAM Extraction : YesRAM Style : AutoROM Extraction : YesROM Style : AutoMux Extraction : YESDecoder Extraction : YESPriority Encoder Extraction : YESShift Register Extraction : YESLogical Shifter Extraction : YESXOR Collapsing : YESResource Sharing : YESMultiplier Style : autoAutomatic Register Balancing : No---- Target OptionsAdd IO Buffers : YESGlobal Maximum Fanout : 500Add Generic Clock Buffer(BUFG) : 8Register Duplication : YESEquivalent register Removal : YESSlice Packing : YESPack IO Registers into IOBs : auto---- General OptionsOptimization Goal : SpeedOptimization Effort : 1Keep Hierarchy : NOGlobal Optimization : AllClockNetsRTL Output : YesWrite Timing Constraints : NOHierarchy Separator : /Bus Delimiter : <>Case Specifier : maintainSlice Utilization Ratio : 100Slice Utilization Ratio Delta : 5---- Other Optionslso : light.lsoRead Cores : YEScross_clock_analysis : NOverilog2001 : YESsafe_implementation : NoOptimize Instantiated Primitives : NOuse_clock_enable : Yesuse_sync_set : Yesuse_sync_reset : Yesenable_auto_floorplanning : No==================================================================================================================================================* HDL Compilation *=========================================================================Compiling verilog file "light.v"Module <light> compiledNo errors in compilationAnalysis of file <"light.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <light>.Module <light> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================INFO:Xst:1304 - Contents of register <dir> in unit <light> never changes during circuit operation. The register is replaced by logic.Synthesizing Unit <light>. Related source file is "light.v". Found finite state machine <FSM_0> for signal <led>. ----------------------------------------------------------------------- | States | 10 | | Transitions | 10 | | Inputs | 0 | | Outputs | 9 | | Clock | clk (rising_edge) | | Clock enable | done (positive) | | Reset | reset (positive) | | Reset type | synchronous | | Reset State | 00000000 | | Power Up State | 00000000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Summary: inferred 1 Finite State Machine(s).Unit <light> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Analyzing FSM <FSM_0> for best encoding.Optimizing FSM <FSM_0> on signal <led[1:5]> with johnson encoding.---------------------- State | Encoding---------------------- 00000000 | 00000 10000000 | 00001 11000000 | 00011 11100000 | 00111 01110000 | 01111 00111000 | 11111 00011100 | 11110 00000111 | 11100 00000011 | 11000 00000001 | 10000----------------------Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# FSMs : 1# Registers : 5 1-bit register : 5==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <light> ...Loading device for application Rf_Device from file '3s400.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block light, actual ratio is 0.=========================================================================* Final Report *=========================================================================Final ResultsRTL Top Level Output File Name : light.ngrTop Level Output File Name : lightOutput Format : NGCOptimization Goal : SpeedKeep Hierarchy : NODesign Statistics# IOs : 11Cell Usage :# BELS : 9# INV : 1# LUT3 : 3# LUT4 : 5# FlipFlops/Latches : 5# FDRE : 5# Clock Buffers : 1# BUFGP : 1# IO Buffers : 10# IBUF : 2# OBUF : 8=========================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-5 Number of Slices: 5 out of 3584 0% Number of Slice Flip Flops: 5 out of 7168 0% Number of 4 input LUTs: 8 out of 7168 0% Number of bonded IOBs: 11 out of 141 7% Number of GCLKs: 1 out of 8 12% =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 5 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -5 Minimum period: 2.814ns (Maximum Frequency: 355.315MHz) Minimum input arrival time before clock: 2.390ns Maximum output required time after clock: 7.896ns Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default period analysis for Clock 'clk' Clock period: 2.814ns (frequency: 355.315MHz) Total number of paths / destination ports: 5 / 5-------------------------------------------------------------------------Delay: 2.814ns (Levels of Logic = 1) Source: led_FFd1 (FF) Destination: led_FFd5 (FF) Source Clock: clk rising Destination Clock: clk rising Data Path: led_FFd1 to led_FFd5 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDRE:C->Q 6 0.626 0.853 led_FFd1 (led_FFd1) INV:I->O 1 0.479 0.681 led_FFd5-In1_INV_0 (led_FFd5-In) FDRE:D 0.176 led_FFd5 ---------------------------------------- Total 2.814ns (1.281ns logic, 1.533ns route) (45.5% logic, 54.5% route)=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Total number of paths / destination ports: 10 / 10-------------------------------------------------------------------------Offset: 2.390ns (Levels of Logic = 1) Source: reset (PAD) Destination: led_FFd5 (FF) Destination Clock: clk rising Data Path: reset to led_FFd5 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 5 0.715 0.783 reset_IBUF (reset_IBUF) FDRE:R 0.892 led_FFd4 ---------------------------------------- Total 2.390ns (1.607ns logic, 0.783ns route) (67.2% logic, 32.8% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Total number of paths / destination ports: 29 / 8-------------------------------------------------------------------------Offset: 7.896ns (Levels of Logic = 2) Source: led_FFd3 (FF) Destination: led1 (PAD) Source Clock: clk rising Data Path: led_FFd3 to led1 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDRE:C->Q 7 0.626 1.201 led_FFd3 (led_FFd3) LUT4:I0->O 1 0.479 0.681 led81 (led8_OBUF) OBUF:I->O 4.909 led8_OBUF (led8) ---------------------------------------- Total 7.896ns (6.014ns logic, 1.882ns route) (76.2% logic, 23.8% route)=========================================================================CPU : 5.91 / 6.39 s | Elapsed : 6.00 / 6.00 s --> Total memory usage is 102080 kilobytesNumber of errors : 0 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 1 ( 0 filtered)⌨️ 快捷键说明
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