rom2_labirint.syr

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Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: rom2_labirint.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "rom2_labirint.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "rom2_labirint"
Output Format                      : NGC
Target Device                      : xc3s400-5-pq208

---- Source Options
Top Module Name                    : rom2_labirint
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : rom2_labirint.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/ASIC设计/zoumigong/rom2_labirint.vhd" in Library work.
Entity <rom2_labirint> compiled.
Entity <rom2_labirint> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <rom2_labirint> (Architecture <Behavioral>).
WARNING:Xst:790 - "D:/ASIC设计/zoumigong/rom2_labirint.vhd" line 188: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "D:/ASIC设计/zoumigong/rom2_labirint.vhd" line 188: Index value(s) does not match array range, simulation mismatch.
Entity <rom2_labirint> analyzed. Unit <rom2_labirint> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <rom2_labirint>.
    Related source file is "D:/ASIC设计/zoumigong/rom2_labirint.vhd".
    Found 30x39-bit ROM for signal <$n0083>.
    Found 1-bit 40-to-1 multiplexer for signal <char<0>>.
    Summary:
	inferred   1 ROM(s).
	inferred   1 Multiplexer(s).
Unit <rom2_labirint> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 30x39-bit ROM                     : 1
# Multiplexers                     : 1
 1-bit 40-to-1 multiplexer         : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <rom2_labirint> ...
Loading device for application Rf_Device from file '3s400.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block rom2_labirint, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : rom2_labirint.ngr
Top Level Output File Name         : rom2_labirint
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 15

Macro Statistics :
# ROMs                             : 1
#      30x39-bit ROM               : 1
# Multiplexers                     : 1
#      1-bit 40-to-1 multiplexer   : 1

Cell Usage :
# BELS                             : 158
#      GND                         : 1
#      LUT3                        : 24
#      LUT4                        : 78
#      MUXF5                       : 47
#      MUXF6                       : 5
#      MUXF7                       : 2
#      MUXF8                       : 1
# IO Buffers                       : 15
#      IBUF                        : 12
#      OBUF                        : 3
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-5 

 Number of Slices:                      52  out of   3584     1%  
 Number of 4 input LUTs:               102  out of   7168     1%  
 Number of bonded IOBs:                 15  out of    141    10%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 13.233ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 397 / 2
-------------------------------------------------------------------------
Delay:               13.233ns (Levels of Logic = 8)
  Source:            row<2> (PAD)
  Destination:       char<0> (PAD)

  Data Path: row<2> to char<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            73   0.715   2.070  row_2_IBUF (row_2_IBUF)
     LUT4:I0->O            1   0.479   0.851  Mrom__n0083_inst_mux_f5_4_SW0 (N42)
     LUT3:I1->O            1   0.479   0.740  Mrom__n0083_inst_mux_f5_4 (_n0083<4>)
     LUT3:I2->O            1   0.479   0.000  col<0>3 (MUX_BLOCK_N20)
     MUXF5:I1->O           1   0.314   0.000  col<1>_rn_2 (MUX_BLOCK_col<1>_MUXF51)
     MUXF6:I0->O           1   0.298   0.740  col<2>_rn_0 (MUX_BLOCK_col<2>_MUXF6)
     LUT3:I2->O            1   0.479   0.681  col<5>1 (char_0_OBUF)
     OBUF:I->O                 4.909          char_0_OBUF (char<0>)
    ----------------------------------------
    Total                     13.233ns (8.152ns logic, 5.081ns route)
                                       (61.6% logic, 38.4% route)

=========================================================================
CPU : 7.59 / 8.00 s | Elapsed : 8.00 / 8.00 s
 
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Total memory usage is 105280 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    2 (   0 filtered)
Number of infos    :    0 (   0 filtered)